l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet
l-fw322-06-db
Related parts for l-fw322-06-db
l-fw322-06-db Summary of contents
Page 1
... Mbits/s traffic — Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders — While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port — Does not require external filter capacitor for PLL — ...
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... PCI Power Management Capabilities Pointer Register ....................................................................................31 Interrupt Line and Pin Register .........................................................................................................................32 MIN_GNT and MAX_LAT Register...................................................................................................................32 PCI OHCI Control Register...............................................................................................................................33 Capability ID and Next Item Pointer Register ...................................................................................................33 Power Management Capabilities Register........................................................................................................34 Power Management Control and Status Register ............................................................................................35 Power Management CSR PCI-to-PCI Bridge Support Extensions ...................................................................36 Power Management Data ...
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... PHY Core Register Map ...................................................................................................................................75 PHY Core Register Fields.................................................................................................................................76 Crystal Selection Considerations............................................................................................................................ 81 Load Capacitance.............................................................................................................................................81 Adjustment to Crystal Loading..........................................................................................................................81 Crystal/Board Layout ........................................................................................................................................81 Serial EEPROM Interface....................................................................................................................................... 82 ac Characteristics of Serial EEPROM Interface Signals ........................................................................................ 82 NAND Tree Testing ................................................................................................................................................ 85 Solder Reflow and Handling ................................................................................................................................... 87 Absolute Maximum Voltage/Temperature Ratings ................................................................................................. 87 Electrical Characteristics ........................................................................................................................................ 88 Timing Characteristics ............................................................................................................................................ 90 Outline Diagrams.................................................................................................................................................... 91 120-Pin TQFP ...
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... Table 5. PCI Command Register Description ........................................................................................................ 25 Table 6. PCI Status Register ................................................................................................................................. 26 Table 7. Class Code and Revision ID Register Description .................................................................................. 27 Table 8. Latency Timer and Class Cache Line Size Register Description ........................................................... 28 Table 9. Header Type and BIST Register Description .......................................................................................... 28 Table 10. OHCI Base Address Register Description ............................................................................................. 29 Table 11. CardBus Base Address Register Description ........................................................................................ 30 Table 12 ...
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... Table 67. PHY Core Register Fields ..................................................................................................................... 76 Table 68. PHY Core Register Page 0: Port Status Page ...................................................................................... 78 Table 69. PHY Core Register Port Status Page Fields ........................................................................................ 79 Table 70. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 80 Table 71. PHY Core Register Vendor Identification Page Fields .......................................................................... 80 Table 72. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 82 Table 73 ...
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... BUS CORE ROM I/F FW322 Functional Description The FW322 is comprised of four major functional sections (see Figure 1): PCI core, OHCI isochronous and asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major sections OHCI ASYNCHRONOUS DATA ...
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... PCI BUS PCI Core The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow the FW322 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or reception, the PCI core arbitrates for the PCI bus and enables the FW322 to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory ...
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... The PCI interface provides an interface between the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the OHCI core and select data from appropriate sources ...
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... Fetch a descriptor block from host memory. 2. Fetch data specified by the descriptor block from host memory and place it into the isochronous transmit FIFO. 3. Data in FIFO is read by the link and sent to the PHY core device interface. Isochronous Receive DMA (IRDMA) The isochronous receive DMA (IRDMA) module moves data from the isochronous receive FIFO to host memory ...
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... Fetch complete buffer descriptor block from host memory. 2. Get data from system memory and store into asynchronous transmit (AT) FIFO. 3. Request transfer of data from FIFO to the link core. 4. Handle retries, if any. 5. Handle errors in steps End the transfer if there are no errors. ...
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... Isochronous Control Timer: contains the logic for the 1394 cycle timer. DataMUX: pipes 1394 data to and from various modules. Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the PCI core. PHY-Link Interface: interfaces with the 1394 physical layer. ...
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... Based on data received from the OHCI block, the link will form packet headers for the 1394 bus. The link will alert the PHY core regarding the availability of the outbound data the link’s function to generate CRC for the outbound data ...
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... The PHY/link interface is a direct connection and does not provide isolation. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49.152 MHz system clock. ...
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... SelfID packets table in Section 4.3.4.1 of the IEEE 1394-1995 and 1394a-2000 standards for additional details example, for a Power_Class value of 001, PC0 = 0, PC1 = 0, and PC2 = 1. When the power supply of the PHY core is removed while the twisted-pair cables are connected, the PHY ...
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... PCI_AD[24 PCI_CBEN[3] 28 PCI_IDSEL 29 PCI_AD[23] 30 Note: Active-low signals within this document are indicated following the symbol names. Agere Systems Inc. PCI PHY/Link Open Host Controller Interface PIN #1 IDENTIFIER Figure 6. Pin Assignments for the FW322 06 FW322 06 1394a 90 V SSA 89 CPS ...
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... PCI_CBEN[3] 29 PCI_IDSEL 30 PCI_AD[23] 31 PCI_AD[22] * Active-low signals within this document are indicated following the symbol names Type O Cable Not Active. CNA output is provided for use in legacy power management systems. CNA is asserted high when none of the PHY ports is receiving an incoming bias voltage. This circuit remains active during the powerdown mode ...
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... PCI_AD[6] 71 PCI_AD[ PCI_AD[4] 74 PCI_AD[3] 75 PCI_AD[2] * Active-low signals within this document are indicated following the symbol names. Agere Systems Inc. PCI PHY/Link Open Host Controller Interface Type — Digital Power. — Digital Ground. I/O PCI Address/Data Bit. I/O PCI Address/Data Bit. ...
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... PCI Local Bus Specification, Rev. 2.2, Sec- tion 4.1.1), connect this pin to the VI/O pin. For Cardbus applica- tions, connect this pin to 3.3 V. For other cases, connect this pin to 3.3 V for PCI buses using 3.3 V signaling for PCI buses using 5 V signaling. I Contender ...
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... TPB0+ 102 TPA0– 103 TPA0+ 104 TPBIAS0 * Active-low signals within this document are indicated following the symbol names. Agere Systems Inc. PCI PHY/Link Open Host Controller Interface Type — Analog Circuit Ground. All V a low-impedance ground plane. — ...
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... Active-low signals within this document are indicated following the symbol names. Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. ...
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... Active-low signals within this document are indicated following the symbol names. Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. ...
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... Reserved † Maximum Latency Minimum Grant [18h] [0Ch minor revision number of the FW322 06 and may be any value from 0 hex to F hex. † Values for this register can be loaded from a serial EEPROM during the powerup sequence. 22 Description Vendor ID [11C1h] Command [0000h] Revision ID [6xh] † ...
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... Pmcsr_bse [00h minor revision number of the FW322 06 and may be any value from 0 hex to F hex. † Values for this register can be loaded from a serial EEPROM during the powerup sequence. ‡ Value for this register is affected by the state of the VAUX_PRESENT input pin. ...
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... Offset: 00h Default: 11C1h Type: Read only Reference: PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 Device ID Register The Device ID register contains a value assigned to the FW322 by Agere. The device identification for the FW322 is 5811h. Offset: 02h Default: 5811h Type: Read only Reference: PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 ...
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... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) PCI Command Register The Command register provides control over the FW322 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification the following bit descriptions. Offset: 04h Default: ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface Internal Registers (continued) PCI Status Register The Status register provides status information for PCI bus related events. All bit functions adhere to the definitions in the PCI Local Bus Specification, v.2.2, Table 6.2. Offset: 06h Default: 0290h ...
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... SUBCLASS 15:8 PGMIF 7:0 CHIPREV * minor revision number of the FW322 06 and may be any value from 0 hex to F hex. Agere Systems Inc. PCI PHY/Link Open Host Controller Interface R Base Class. This field returns 0Ch when read, which classifies the func- tion as a serial bus controller. ...
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... The Latency Timer and Class Cache Line Size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the FW322 serial EEPROM is detected, then the contents of this register are loaded from the serial EEPROM interface after a PCI reset serial EEPROM is detected, then this register returns a default value of 0000h. ...
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... The OHCI Base Address register is programmed with a base address referencing the memory-mapped OHCI con- trol. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4 Kbytes of mem- ory address space are required for the OHCI registers. ...
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... The CardBus Base Address register is programmed with a base address referencing the memory-mapped Function Event registers. When BIOS writes all 1s to this register, the value read back is FFFF FF00h, indicating that 256 bytes of memory address space are required for the CardBus Function Event registers. ...
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... EEPROM is not interfaced to the FW322 06, bit 0 (SubSystemWriteEn) of the PCI Config register, offset 4Ch can be set to enable writes to the PCI Subsystem ID and PCI Subsystem Vendor ID so that these registers can be customized to the correct ID values. After the IDs have been written, the SubSystemWriteEn bit should be reset to protect the data from being overwritten ...
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... The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the Latency Timer register serial EEPROM is detected, then the contents of this register are loaded from the serial EEPROM interface after a PCI reset serial EEPROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 0Ch, MAX_LAT = 18h. ...
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... Internal Registers (continued) PCI OHCI Control Register The PCI OHCI Control register is defined in Section A.3.7 of the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. Note that the GLOBAL_SWAP bit is loaded from the serial EEPROM on powerup. Offset: 40h ...
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... FFC2h. If the VAUX_PRESENT input pin is deasserted when the FW322 comes out of powerup reset, then the default value of this register will be 7E02h. In addition, the default value of this register can be selectively pro- grammed by the serial EEPROM. Note, however, that if VAUX_PRESENT is deasserted, then the D3cold and AUX_PWR fields will both be set to 0h regardless of the serial EEPROM settings ...
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... This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. The value of this register after a PCI reset is dependent on whether the FW322 is enabled to generate a PME event while in the D3cold state. If the PME_D3cold bit within the Power Management Capabilities register is asserted, then the PME_STS and PME_ENB bits within this register will not be reset by a PCI reset, i ...
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... EEPROM and vice versa. This is to comply with the PCI Specification, which states that these two functions must be implemented mutually exclusive of one another. The FW322 does not enforce this, and therefore the creator of the serial EEPROM image to ensure that these two fields are used mutually exclusive of one another. ...
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... RegisterSet causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding bit unaffected bit written to RegisterClear causes the corresponding bit in the register to be reset, while a 0 bit leaves the corresponding bit unaffected. Typically, a read from either RegisterSet or RegisterClear returns the con- tents of the set or clear register ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 19. OHCI Register Map (continued) DMA Register Name Context SelfID SelfID Buffer SelfID Count Reserved — Isochronous Receive Channel Mask High Isochronous Receive Channel Mask Low Interrupt Event Interrupt Mask ...
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... Context Control Context 0:7 Reserved Command Pointer Isochronous Context Control Receive Context n Reserved n = 0:7 Command Pointer Context Match Reserved Agere Systems Inc. PCI PHY/Link Open Host Controller Interface Abbreviation Offset ContextControlSet 180h ContextControlClear 184h — 188h CommandPtr 18Ch — 190h:19Ch ContextControlSet 1A0h ...
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... OHCI Version Register This register indicates the OHCI version supported, and whether or not the serial EEPROM is present. To support backwards compatibility with existing hardware and software, the version and revision fields default to 8’h01 and 8’h00 respectively. These values denote compatibility with version 1.0 of the OHCI specification. However, both the version and revision fields are programmable via the serial EEPROM. This functionality allows these fields to be optionally updated to 8’ ...
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... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) GUID ROM Register The GUID ROM register is used to access the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI Version register is set. Offset: 04h Default: 00XX 0000h Reference: 1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.3 Table 21 ...
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... CSR Compare Register The CSR Compare register is used to access the bus management CSR registers from the host through compare- swap operations. This register contains the data to be compared with the existing value of the CSR resource. Offset: 10h Default: XXXX XXXXh Reference: 1394 Open Host Controller Interface Specification, Rev ...
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... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) Configuration ROM Header Register The Configuration ROM Header register externally maps to the first quadlet of the 1394 configuration ROM, offset 48’hFFFF_F000_0400. Offset: 18h Default: 0000 0000h Reference: 1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.2 Table 26 ...
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... Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.3 Table 27. Bus Identification Register Description Bit Field Name 31—0 busID Bus Options Register The Bus Options register externally maps to the second quadlet of the Bus_Info_Block and is 1394 addressable at FFFF_F000_0408. Offset: 20h Default: 0000 A002h Reference: 1394 Open Host Controller Interface Specification, Rev ...
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... EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a PCI reset serial EEPROM is detected, then the contents of this register can be loaded with a single PCI write to either of two configuration registers, executed after a PCI reset. The two configuration registers are located at offset 0x70, for all CardBus and new PCI applications, and offset 0x80, for backward compatibility with FW322 05 PCI applications only ...
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... The Configuration ROM Mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. Offset: 34h Default: 0000 0000h Reference: 1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.6 Table 31. Configuration ROM Mapping Register Description Bit Field Name 31:10 configROMaddr 9:0 ...
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... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) Posted Write Address Low Register The Posted Write Address Low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Offset: 38h Default: XXXX XXXXh Reference: 1394 Open Host Controller Interface Specification, Rev ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Host Controller Control Register The Host Controller Control set/clear register pair provides flags for controlling the OHCI portion of the FW322. Offset: 50h set register 54h clear register Default: X00X 0000h Reference: 1394 Open Host Controller Interface Specification, Rev ...
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... PCI PHY/Link Open Host Controller Interface Type RSU This bit is cleared either a hardware or software reset. Soft- ware must set this bit to 1 when the system is ready to begin oper- ation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready ...
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... PCI PHY/Link Open Host Controller Interface Internal Registers (continued) SelfID Buffer Pointer Register The SelfID Buffer Pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the SelfID packets are stored during bus initialization. Bits 31:11 are read/write accessible. Offset: 64h ...
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... Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register The Isochronous Receive Multiple Channel Mask High set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the Isochronous Receive Multiple Channel Mask High register. ...
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... The only mechanism to clear the bits in this register is to write the corresponding bit in the clear register. Reading the IntEventSet register returns the current state of the IntEvent register. Reading the IntEventClear register returns the masked version of the IntEvent register, i ...
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... Indicates the PHY core requests an interrupt through a status transfer. RSCU Indicates that an OHCI register access failed due to a missing SCLK clock signal from the PHY. When a register access fails, this bit will be set before the next register access. RSCU Indicates that the PHY core chip has entered bus reset mode. ...
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... The Interrupt Mask set/clear register is used to enable/disable the various FW322 interrupt sources. Reads from either the set register or the clear register always return the contents of the Interrupt Mask register. In all cases except masterIntEnable (bit 31), the enables for each interrupt event align with the Interrupt Event (IntEvent) register bits (see Table 40) ...
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... Table 41Interrupt Mask Register Description (continued) Bit Field Name 9 lockRespErr 8 postedWriteErr 7 isochRx 6 isochTx 5 RSPkt 4 RQPkt 3 ARRS 2 ARRQ 1 respTxComplete 0 reqTxComplete Agere Systems Inc. PCI PHY/Link Open Host Controller Interface Type RSCU When set, these bits enable the corresponding IntEvent register bits to generate a processor interrupt. FW322 06 1394a Description 55 ...
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... The interrupt bits are set by an asserting edge of the corresponding interrupt signal writing the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write the corresponding bit in the clear register. ...
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... The Isochronous Transmit Interrupt Mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register, always return the contents of the Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event align with the event register bits detailed in Table 42 ...
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... The interrupt bits are set by an asserting edge of the corresponding interrupt signal writing the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write the corresponding bit in the clear reg- ister. ...
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... The Isochronous Receive Interrupt Mask set/clear register is used to enable the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event correspond to the isoRecvIntEvent register bits ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Link Control Register The Link Control register provides flags to enable and configure the link core cycle timer and receiver portions of the FW322. Offset: E0h set register E4h clear register Default: ...
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... Node Identification Register The Node Identification register contains the address of the node on which the OHCI resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15:6) and the NodeNumber field (bits 5:0) is referred to as the node ID. Offset: ...
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... When the FW322 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. ...
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... Table 51. Asynchronous Request Filter Low Register Description Bit Field Name Type 31:0 asynReqResourceN RSCU If this bit is set for local bus node number N (where N = the bit number from Agere Systems Inc. PCI PHY/Link Open Host Controller Interface Description nonlocal bus nodes are accepted and the values of all asynReqResourceN bits will be ignored ...
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... IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the ARRQ context instead of the physical request context. ...
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... Data Sheet, Rev. 1 December 2005 Internal Registers (continued) Asynchronous Context Control Register The Asynchronous Context Control set/clear register controls the state and indicates status of the DMA context. Offset: 180h set register (ATRQ) 184h clear register (ATRQ) 1A0h set register (ATRS) 1A4h ...
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... PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Asynchronous Context Command Pointer Register The Asynchronous Context Command Pointer register contains a pointer to the address of the first descriptor block that the FW322 accesses when software enables the context by setting the Asynchronous Context Control register bit 15 (run). Offset: ...
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... Isochronous Transmit Context Control (IT DMA ContextControl) Register The Isochronous Transmit Context Control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7). Offset: 200h + ( set register ...
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... The Isochronous Transmit Context Command Pointer register contains a pointer to the address of the first descrip- tor block that the FW322 accesses when software enables an isochronous transmit context by setting the Isochro- nous Transmit Context Control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7). ...
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... Channel Mask registers. If more than one Isochronous Receive Context Control register has this bit set, then results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. RSC When this bit is set, received packets are separated into first and second payload and streamed independently to the first buffer series and second buffer series (see OHCI v ...
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... Isochronous Receive Context Command Pointer Register The Isochronous Receive Context Command Pointer register contains a pointer to the address of the first descriptor block that the FW322 accesses when software enables an isochronous receive context by setting the Isochronous Receive Context Control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7) ...
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... December 2005 Internal Registers (continued) Isochronous Receive Context Match (IR DMA ContextMatch) Register The Isochronous Receive Context Match register is used to control on which isochronous cycle the context should start. The register is also used to control which packets are accepted by the context. Offset: 410Ch + ( ...
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... The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO constraints, and the PCI cache line size. ...
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... The fields in this register control the functionality within the asynchronous and physical DMA engines. Accesses to the PCI bus and how much data the DMA engines will attempt to move in a single PCI transaction can be con- trolled. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO con- straints, and the PCI cache line size ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Link Options The values in this register provide low-level control of configurable features within the FW322 that are beyond those stated in 1394 and OHCI specifications. Offset: 840h Default: 0000 0020h Table 64. Link Options Register Description ...
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... Data Sheet, Rev. 1 December 2005 Internal Register Configuration PHY Core Register Map The PHY Core register map is shown below in Table 65. Reference: IEEE Standard 1394a-2000, Annex J2 Table 65. PHY Core Register Map Address Bit 0 Bit 1 0000 2 0001 RHB IBR 2 0010 Extended (7) 2 0011 ...
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... SelfID packet 0, which will be the logi- cal AND of this bit and LPS active. See Cleared or set by software to control the value of the C bit transmit- ted in the SelfID packet. Powerup reset value is set by the FW322’s description CONTENDER pin. ...
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... Loop Detect. A write of one to this bit clears it to zero. 1 Cable Power Failure Detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. 0 Arbitration State Machine Time-Out. A write of one to this bit clears it to zero (see MAX_ARB_STATE_TIME). ...
Page 78
... Internal Register Configuration The port status page is used to access configuration and status information for each of the PHY core’s ports. The port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY Core register at address 0111 . The format of the port status page is illustrated by Table 67 below; reserved fields are shown as 2 XXXXX ...
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... Data Sheet, Rev. 1 December 2005 Internal Register Configuration The meaning of the register fields in the port status page are defined by Table 68 below. Table 68. PHY Core Register Port Status Page Fields Field Size Type AStat 2 R BStat 2 R Child 1 R Connected 1 R Bias ...
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... Size Type Compliance_level 8 r Vendor_ID 24 r Product_ID minor revision number of the FW322 06 and may be any value from 0 hex to F hex. Note: The vendor-dependent page provides access to information used in the manufacturing test of the FW322 (continued) Contents Bit 2 Bit 3 Bit 4 Compliance_level ...
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... Minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals. Agere Systems Inc. ...
Page 82
... EEPROM. ROM_AD is bidirectional and is used for serial data/control transfers between the FW322 and the external EEPROM. The FW322 uses this interface to read the contents of the serial EEPROM in response to the first PCI reset after powerup. The FW322 also makes the serial ROM interface visible to software through the OHCI defined GUID ROM register ...
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... ROM_AD IN tDATA_VALID ROM_AD OUT ROM_CLK: serial clock, ROM_AD: serial data I/O. ROM_CLK ROM_AD 8TH BIT WORD n ROM_CLK: serial clock, ROM_AD: serial data I/O. ROM_AD ROM_CLK ROM_CLK: serial clock, ROM_AD: serial data I/O. Agere Systems Inc. PCI PHY/Link Open Host Controller Interface tPW_LOW tPW_HIGH tPW_LOW ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface ac Characteristics (continued) ROM_AD ROM_CLK ROM_CLK: serial clock, ROM_AD: serial data I/O. ROM_CLK DATA IN DATA OUT START ROM_CLK: serial clock. 84 START Figure 11. Start and Stop Definition 1 Figure 12. Output Acknowledge Data Sheet, Rev. 1 December 2005 STOP 1311 (F) R ...
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... When NAND tree is enabled, the NAND tree logic follows the signal ordering in the following table. To run the test, force all of the inputs in the table below high. At this point, the NAND tree output should be verified to be high. In the order listed below, force each input low, while keeping previously tested inputs low. After each input is forced low, the NAND tree output should be verified, and the correct value should be the opposite of the previous value ...
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... FW322 06 1394a PCI PHY/Link Open Host Controller Interface NAND Tree Testing (continued) Table 72. NAND Tree Testing (continued) Input Pin # Pin Order Name 51 26 PCI_AD[24 PCI_AD[25 PCI_AD[26 PCI_AD[27 PCI_AD[28 PCI_AD[29 PCI_AD[30 PCI_AD[31 PCI_CLK CARDBUSN ...
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... Up to three reflows may be performed using a temperature profile that meets the requirements of Table 3 in stan- dard IPC/JEDEC J-STD-020. The requirements of IPC/JEDEC J-STD-033 must be met. The maximum allowable body temperature for the FW322 is 220 °C —225 °C. This is the actual tolerance that Agere uses to test the devices during preconditioning. ...
Page 88
... Common-mode Voltage Nonsource Power Mode* Receive Input Jitter Receive Input Skew Between TPA and TPB cable inputs, Between TPA and TPB cable inputs, Between TPA and TPB cable inputs, Positive Arbitration Comparator Input Threshold Voltage Negative Arbitration Comparator Input Threshold Voltage ...
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... TPA+, TPA−, TPB+, TPB− Common-mode Speed Signaling Current, TPB+, TPB− * Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver currents. Table 76. Device Characteristics Parameter ...
Page 90
... FW322 06 1394a PCI PHY/Link Open Host Controller Interface Timing Characteristics Table 77. Switching Characteristics Symbol Parameter — Jitter, Transmit — Transmit Skew t Rise Time, Transmit (TPA/TPB Fall Time, Transmit (TPA/TPB) f Table 78. Clock Characteristics Parameter External Clock Source Frequency 90 90 Measured Test Conditions ...
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... BSC 14.00 BSC 120 DETAIL A 0.40 BSC Ordering Information Device Code FW322 06 L-FW322-06- effort to better serve its customers and the environment, Agere is converting to lead-free material set on this product. Agere Systems Inc. PCI PHY/Link Open Host Controller Interface 91 90 14.00 BSC 61 60 DETAIL B 1 ...
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... EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. ...