l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 53

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Table 40. Interrupt Event Register Description (continued)
Agere Systems Inc.
14:10
Bit
21
20
19
18
17
16
15
9
8
7
6
5
4
3
2
1
0
SelfIDcomplete2
respTxComplete
cycle64Seconds
reqTxComplete
selfIDcomplete
postedWriteErr
regAccessFail
lockRespErr
Field Name
cycleSynch
Reserved
busReset
isochRx
isochTx
RSPkt
RQPkt
ARRQ
ARRS
PHY
(continued)
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Type
RU
RU
R
Indicates that the seventh bit of the cycleSeconds (see Table 49)
counter has changed.
Indicates that a new isochronous cycle has started. This bit is set when
the low-order bit of the cycleCount (see Table 49) toggles.
Indicates the PHY core requests an interrupt through a status transfer.
Indicates that an OHCI register access failed due to a missing SCLK
clock signal from the PHY. When a register access fails, this bit will be
set before the next register access.
Indicates that the PHY core chip has entered bus reset mode.
A SelfID packet stream has been received. It is generated at the end of
the bus initialization process. This bit is turned off simultaneously when
bit 17 (busReset) is turned on.
Secondary indication of the end of a SelfID packet stream. This bit will
be set by the OHCI when it sets SelfIDcomplete, and will retain state
independent of the busReset bit of this register.
Reserved. Bits 14:10 return 0s when read.
Indicates that the FW322 sent a lock response for a lock request to a
serial bus register, but did not receive an ack_complete.
Indicates that a host bus error occurred while the FW322 was trying to
write a 1394 write request, which had already been given an
ack_complete, into system memory.
Isochronous Receive DMA Interrupt. Indicates that one or more
isochronous receive contexts have generated an interrupt. This is not a
latched event; it is the ORing of all bits in the Isochronous Receive
Interrupt Event and Isochronous Receive Interrupt Mask registers. The
Isochronous Receive Interrupt Event register (see Table 44) indicates
which contexts have interrupted.
Isochronous Transmit DMA Interrupt. Indicates that one or more
isochronous transmit contexts have generated an interrupt. This is not
a latched event; it is the ORing of all bits in the Isochronous Transmit
Interrupt Event (see Table 42) and Isochronous Transmit Interrupt
Mask (see Table 43) registers. The Isochronous Transmit Interrupt
Event register indicates which contexts have interrupted.
Indicates that a packet was sent to an asynchronous receive response
context buffer and the descriptor’s xferStatus and resCount fields have
been updated.
Indicates that a packet was sent to an asynchronous receive request
context buffer and the descriptor’s xferStatus and resCount fields have
been updated.
Asynchronous Receive Response DMA Interrupt. This bit is condi-
tionally set upon completion of an ARRS DMA context command
descriptor.
Asynchronous Receive Request DMA Interrupt. This bit is condi-
tionally set upon completion of an ARRQ DMA context command
descriptor.
Asynchronous Response Transmit DMA Interrupt. This bit is condi-
tionally set upon completion of an ATRS DMA command.
Asynchronous Request Transmit DMA Interrupt. This bit is condi-
tionally set upon completion of an ATRQ DMA command.
PCI PHY/Link Open Host Controller Interface
Description
FW322 06 1394a
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