l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 14

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
FW322 Functional Description
An external resistor sets the driver output current,
along with other internal operating currents. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ ± 1%.
Four signals are used as inputs to set four
configuration status bits in the self-identification
(SelfID) packet. These signals are hardwired high or
low as a function of the equipment design. PC[0:2] are
the three signals that indicate either the need for
power from the cable or the ability to supply power to
the cable. The fourth signal (CONTENDER), as an
input, indicates whether a node is a contender for bus
manager. When the CONTENDER signal is asserted,
it means the node is a contender for bus manager.
When the signal is not asserted, it means that the
node is not a contender. The contender bit
corresponds to the c field (bit 20) in the SelfID packet.
PC[0:2] corresponds to the pwr field of the SelfID
packet in the following manner: PC0 corresponds to bit
21, PC1 corresponds to bit 22, and PC2 corresponds
to bit 23 (see SelfID packets table in Section 4.3.4.1 of
the IEEE 1394-1995 and 1394a-2000 standards for
additional details). As an example, for a Power_Class
value of 001, PC0 = 0, PC1 = 0, and PC2 = 1.
When the power supply of the PHY core is removed
while the twisted-pair cables are connected, the PHY
core transmitter and receiver circuitry has been
designed to present a high impedance to the cable in
order to not load the TPBIAS signal voltage on the
other end of the cable.
Whenever the TPA±/TPB± signals are wired to a
connector, they must be terminated using the normal
termination network. This is required for reliable
operation. For those applications when one or more of
the FW322 ports are not wired to a connector, those
unused ports may be left unconnected without normal
termination. When a port does not have a cable
connected, internal connect-detect circuitry will keep
the port in a disconnected state.
14
(continued)
Note: All gap counts on all nodes of a 1394 bus must
The internal link power status (LPS) signal works with
the internal LKON signal to manage the LLC power
usage of the node. The LPS signal indicates if the LLC
of the node is powered up or down. If LPS is inactive
for more than 1.2 µs and less than 25 µs, the internal
PHY/link interface is reset.
If LPS is inactive for greater than 25 µs, the PHY will
disable the internal PHY/link interface to save power.
The FW322 continues its repeater function even when
the PHY/link interface is disabled. If the PHY then
receives a link-on packet, the internal LKON signal is
activated to output a 6.114 MHz signal, which can be
used by the LLC to power itself up. Once the LLC is
powered up, the internal LPS signal communicates this
to the PHY and the internal PHY/link interface is
enabled. The internal LKON signal is turned off when
the LCtrl bit is set. (For more information on this bit,
refer to the Table 66 on PHY Core Register Fields in
this data sheet.)
Three of the FW322 pins are used to set up various
test conditions used only during the device
manufacturing process. These pins are SE, SM, and
PTEST.
be identical. The software accomplishes this by
issuing PHY core configuration packets (see
Section 4.3.4.3 of IEEE 1394-1995 and 1394a-
2000 standards) or by issuing two bus resets,
which resets the gap counts to the maximum
level (3Fh).
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.