l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 20

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information
Table 1. Pin Descriptions (continued)
* Active-low signals within this document are indicated by an N following the symbol names.
Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without
20
20
105
106
107
108
109
110
111
112
113
114
115
116
Pin
normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state.
Symbol*
RESETN
PLLV
PLLV
PTEST
V
V
XO
SM
R0
R1
SE
DDA
SSA
XI
DD
SS
(continued)
Analog I/O
Type
—
—
—
—
I
I
I
I
I
Analog Circuit Ground. All V
low-impedance ground plane.
Analog Circuit Power. V
the device.
Current Setting Resistor. An internal reference voltage is applied to
a resistor connected between R0 and R1 to set the operating current
and the cable driver output current. A low temperature-coefficient
resistor (TCR) with a value of 2.49 kΩ ± 1% should be used to meet
the IEEE 1394-1995 standard requirements for output voltage limits.
Power for PLL Circuit. PLLV
portion of the device.
Ground for PLL Circuit. PLLV
plane.
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel
resonant fundamental mode crystal. Although when a 24.576 MHz
clock source is used, it can be connected to XI with XO left uncon-
nected. The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used. It is necessary to
add an external series resistor to the XO pin. The value of the resistor
is nominally 400 Ω. For more details, refer to the Crystal Selection
Considerations section in this data sheet. Note that it is very impor-
tant to place the crystal as close as possible to the XO and XI pins,
i.e., within 0.5 in./1.27 cm. For more important details regarding the
crystal, refer to the FW323/FW322 Hardware Implementation Design
Guideline Application Note.
Reset (Active-Low). When RESETN is asserted low (active), a 1394
bus reset condition is set on the active cable ports and the FW322 is
reset to the reset start state. To guarantee that the PHY will reset, this
pin must be held low for at least 2 ms. An internal pull-up resistor,
connected to V
(0.1 µF) and resistor (510 kΩ), in parallel, are required to connect this
pin to ground. This circuitry will ensure that the capacitor will be
discharged when PHY power is removed. The input is a standard
logic buffer and can also be driven by an open-drain logic output
buffer. Do not leave this pin unconnected. This pin is also used with
the EEPROM interface. It is the powerup reset pin. This pin is
asserted low (active) to indicate a powerup reset. Refer to the
FW322 06/FW323 06 EEPROM Interface and Start-up Behavior
Application Note sections titled Initiation of EEPROM Load and Initial
Powerup.
Test. Used by Agere for device manufacturing testing. Tie to V
normal operation.
Test Mode Control. SM is used during Agere’s manufacturing test
and should be tied to V
Test Mode Control. SE is used during Agere’s manufacturing test
and should be tied to V
DD
, is provided, so only an external delay capacitor
SS
SS
DDA
for normal operation.
for normal operation.
Description
DD
SSA
supplies power to the analog portion of
SS
supplies power to the PLL circuitry
signals should be tied together to a
is tied to a low-impedance ground
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.
SS
for