l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 22

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers
This section provides a summary of the internal registers within the FW322, including both PCI Configuration regis-
ters and OHCI registers. Register default values, registers, bits that have not been implemented in the FW322, and
other information specific to the FW322 will be noted.
Please refer to the PCI Local Bus Specification v.2.2, PCI Bus Power Management Interface Specification, v.1.1,
1394 OHCI specification v.1.1, and the IEEE standard 1394a-2000 Specification for further details concerning
these registers. Table 2 describes the field access tags that are designated in the Type column of the register
tables in this document.
Table 2. Bit-Field Access Tag Description
PCI Configuration Registers
Table 3 and Table 3 illustrate the PCI configuration header that includes both the predefined portion of the
configuration space and the user-definable registers. Note that there are two mutually exclusive versions of this
header: one for PCI applications (CardBusN = 1) and one for CardBusN applications (CardBusN = 0).
Table 3a . PCI Configuration Register Map, CardBusN = 1
* x is a minor revision number of the FW322 06 and may be any value from 0 hex to F hex.
† Values for this register can be loaded from a serial EEPROM during the powerup sequence.
22
Maximum Latency
Access Tag
BIST [00h]
W
R
C
U
S
[18h]
Subsystem ID
Device ID [5811h]
Status [02901h]
Update Field may be autonomously updated by the FW322.
†
Name
Read
Clear
Write
Set
Class Code [0C0010h]
OHCI Base Address Register [0000 0000h]
Header Type [00h]
†
Minimum Grant
[0000h]
CardBus CIS Pointer [0000 0000h]
Field may be read by software.
Field may be written by software to any value.
Field may be set by a write of 1. Writes of 0 have no effect.
Field may be cleared by a write of 1. Writes of 0 have no effect.
Reserved
[0Ch]
Register Name [Default]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
†
Latency Timer
Interrupt Pin [01h]
Subsystem Vendor ID
Command [0000h]
Vendor ID [11C1h]
†
[00h]
Description
PCI Power Manage-
Interrupt Line [00h]
Revision ID [6xh]
Cache Line Size
ment Capabilities
Pointer [44h]
†
[0000h]
[00h]
†
*
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.
Offset
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h