l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 16

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information
Table 1. Pin Descriptions
* Active-low signals within this document are indicated by an N following the symbol names.
16
16
Pin
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
11
1
2
3
4
5
6
7
8
9
PCI_PMEN/CSTSCHG
PCI_CBEN[3]
PCI_AD[31]
PCI_AD[30]
PCI_AD[29]
PCI_AD[28]
PCI_AD[27]
PCI_AD[26]
PCI_AD[25]
PCI_AD[24]
PCI_AD[23]
PCI_AD[22]
PCI_INTAN
PCI_REQN
PCI_IDSEL
PCI_GNTN
PCI_RSTN
ROM_CLK
CLKRUNN
ROM_AD
PCI_CLK
Symbol*
TEST1
TEST0
CNA
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
SS
(continued)
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
O
O
O
O
I
I
I
I
I
I
Cable Not Active. CNA output is provided for use in legacy power
management systems. CNA is asserted high when none of the PHY
ports is receiving an incoming bias voltage. This circuit remains
active during the powerdown mode. The CNA pin is TTL-compatible.
This pin can source and sink up to a 6 mA load.
Test. Used by Agere for device manufacturing testing. Tie to V
normal operation.
ROM Clock.
ROM Address/Data.
Test. Used by Agere for device manufacturing testing. Tie to V
normal operation.
Digital Power.
Digital Ground.
CLKRUNN (Active-Low). Optional signal for PCI mobile computing
environment. If not used, CLKRUNN pin needs to be pulled down to
V
PCI Interrupt (Active-Low).
PCI Reset (Active-Low).
PCI Grant Signal (Active-Low).
PCI Request Signal (Active-Low).
PCI Power Management Event (Active-Low)/CardBus Status
Changed (Active-High). When the CARDBUSN signal is high (i.e.,
when the FW322 is communicating directly with the PCI bus and not
the CardBus), a PCI power management event will be indicated if
this signal is low. When the CARDBUSN signal is low (indicating the
FW322 is in CardBus mode), this pin signals that the CardBus status
has changed when it is active-high. (See PC Card Standard, v. 8.0,
Volume 2, Section 5.2.11 for more information regarding CSTSCHG.)
Digital Power.
PCI Clock Input. 33 MHz.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Power.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
PCI Command/Byte Enable (Active-Low).
PCI ID Select.
PCI Address/Data Bit.
PCI Address/Data Bit.
SS
for correct operation.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.
SS
SS
for
for