l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 5

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
FW322 06 1394a
December 2005
PCI PHY/Link Open Host Controller Interface
Table of Contents
(continued)
Table
Page
Table 36. Host Controller Control Register Description ......................................................................................... 48
Table 37. SelfID Buffer Pointer Register Description ............................................................................................ 50
Table 38. SelfID Count Register Description ......................................................................................................... 50
Table 39. Isochronous Receive Channel Mask High Register Description ........................................................... 51
Table 40. Isochronous Receive Channel Mask Low Register Description ............................................................ 51
Table 41. Interrupt Event Register Description ...................................................................................................... 52
Table 42. Interrupt Mask Register Description ...................................................................................................... 54
Table 43. Isochronous Transmit Interrupt Event Register Description .................................................................. 56
Table 44. Isochronous Transmit Interrupt Event Description ................................................................................ 57
Table 45. Isochronous Receive Interrupt Event Description ................................................................................. 58
Table 46. Fairness Control Register Description ................................................................................................... 59
Table 47. Link Control Register Description ......................................................................................................... 60
Table 48. Node Identification Register Description ............................................................................................... 61
Table 49. PHY Core Layer Control Register Description ...................................................................................... 62
Table 50. Isochronous Cycle Timer Register Description ..................................................................................... 62
Table 51. Asynchronous Request Filter High Register Description ....................................................................... 63
Table 52. Asynchronous Request Filter Low Register Description ....................................................................... 63
Table 53. Physical Request Filter High Register Description ................................................................................ 64
Table 54. Physical Request Filter Low Register Description ................................................................................. 64
Table 55. Asynchronous Context Control Register Description ........................................................................... 65
Table 56. Asynchronous Context Command Pointer Register Description ........................................................... 66
Table 57. Isochronous Transmit Context Control Register Description ................................................................ 67
Table 58. Isochronous Transmit Context Command Pointer Register Description ............................................... 68
Table 59. Isochronous Receive Context Control Register Description .................................................................. 69
Table 60. Isochronous Receive Context Command Pointer Register Description ................................................ 70
Table 61. Isochronous Receive Context Match Register Description ................................................................... 71
Table 62. FW322 Vendor-Specific Registers Description ..................................................................................... 72
Table 63. Isochronous DMA Control Registers Description .................................................................................. 72
Table 64. Asynchronous DMA Control Registers Description ............................................................................... 73
Table 65. Link Options Register Description ......................................................................................................... 74
Table 66. PHY Core Register Map ........................................................................................................................ 75
Table 67. PHY Core Register Fields ..................................................................................................................... 76
Table 68. PHY Core Register Page 0: Port Status Page ...................................................................................... 78
Table 69. PHY Core Register Port Status Page Fields ........................................................................................ 79
Table 70. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 80
Table 71. PHY Core Register Vendor Identification Page Fields .......................................................................... 80
Table 72. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 82
Table 73. NAND Tree Testing ............................................................................................................................... 85
Table 74. Absolute Maximum Ratings ................................................................................................................... 87
Table 75. Analog Characteristics ........................................................................................................................... 88
Table 76. Driver Characteristics ............................................................................................................................ 89
Table 77. Device Characteristics ........................................................................................................................... 89
Table 78. Switching Characteristics ...................................................................................................................... 90
Table 79. Clock Characteristics ............................................................................................................................. 90
Agere Systems Inc.
5