l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 18

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information
Table 1. Pin Descriptions (continued)
* Active-low signals within this document are indicated by an N following the symbol names.
18
18
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
CONTENDER
MPCIACTN
PCI_AD[1]
PCI_AD[0]
PCI_VIOS
Symbol*
LKON
V
V
PC2
PC1
PC0
CPS
V
LPS
V
V
DDA
SSA
SS
DD
DD
(continued)
Type
I/O
I/O
—
—
—
—
—
—
O
O
O
I
I
I
Digital Ground.
Digital Power.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Signaling Indicator. For PCI applications that use a universal
expansion board (see PCI Local Bus Specification, Rev. 2.2, Sec-
tion 4.1.1), connect this pin to the VI/O pin. For Cardbus applica-
tions, connect this pin to 3.3 V. For other cases, connect this pin to
3.3 V for PCI buses using 3.3 V signaling or to 5 V for PCI buses
using 5 V signaling.
Contender. On hardware reset (RESETN), this input sets the
default value of the CONTENDER bit indicated during SelfID. This
bit can be tied to V
manager or to ground (low) to not be considered for bus manager.
Power-Class Indicators. On hardware reset (RESETN), these
inputs set the default value of the power class indicated during
SelfID. These bits can be tied to V
required for particular power consumption and source characteris-
tics. In SelfID packet (see Section 4.3.4.1 of the 1394 a-2000 Spec-
ification), PC0, the most significant bit of this 3-bit field,
corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corre-
sponds to bit 23. As an example, for a Power_Class value of 001,
PC0 = 0, PC1 = 0, and PC2 = 1.
Link On. Signal from the internal PHY core to the internal link core.
This signal is provided as an output for use in legacy power
management systems.
Link Power Status. Signal from the internal link core to the internal
PHY core. LPS is provided as an output for use in legacy power
management systems.
Mini PCI Function Active. An active-low output used only in Mini
PCI applications. A low indicates that the FW322 requires full
system performance. If MPCIACTN is low, the FW322 requires that
the system not be in a low-power state.
Digital Power.
Cable Power Status. CPS is normally connected to the cable
power through a 400 kΩ resistor. This circuit drives an internal
comparator that detects the presence of cable power. This informa-
tion is maintained in one internal register and is available to the
LLC by way of a register read (see IEEE 1394 a-2000, Standard for
a High Performance Serial Bus, Sections 4.2.2.7 and 5B.1).
Note: This pin can be left unconnected for applications that do not
Analog Circuit Ground. All V
to a low-impedance ground plane.
Analog Circuit Power. V
of the device.
use 1394 bus power (VP). When this pin is grounded, the
PWR_FAIL bit in PHY register 0101
DD
(high), so it will be considered for bus
DDA
Description
supplies power to the analog portion
SSA
DD
signals should be tied together
(high) or to ground (low) as
2
will set.
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.