l-fw322-06-db ETC-unknow, l-fw322-06-db Datasheet - Page 4

• Manufacturer Part Number: l-fw322-06-db
• Description: Phy/link Open Host Controller Interface
• Manufacturer: ETC-unknow

FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Figure
Figure 1. . FW322 Conceptual Block Diagram ........................................................................................................ 6
Figure 2. . PCI Core Block Diagram ........................................................................................................................ 7
Figure 3. . OHCI Core Block Diagram ..................................................................................................................... 8
Figure 4. . Link Core Block Diagram ...................................................................................................................... 11
Figure 5. . The PHY Core Block Diagram .............................................................................................................. 12
Figure 6. . Pin Assignments for the FW322 06 ...................................................................................................... 15
Figure 7. . Crystal Circuitry .................................................................................................................................... 81
Figure 8. . Bus Timing ........................................................................................................................................... 83
Figure 9. . Write Cycle Timing ............................................................................................................................... 83
Figure 10. . Data Validity ....................................................................................................................................... 83
Figure 11. . Start and Stop Definition .................................................................................................................... 84
Figure 12. . Output Acknowledge .......................................................................................................................... 84
Figure 13. Nand Tree Logic Structure ................................................................................................................... 86
Table
Table 1. Pin Descriptions ....................................................................................................................................... 16
Table 2. Bit-Field Access Tag Description ............................................................................................................. 22
Table 3. PCI Configuration Register Map, CardBusN = 1 ..................................................................................... 22
Table 4. PCI Configuration Register Map, CardBusN = 0 ..................................................................................... 23
Table 5. PCI Command Register Description ........................................................................................................ 25
Table 6. PCI Status Register ................................................................................................................................. 26
Table 7. Class Code and Revision ID Register Description .................................................................................. 27
Table 8. Latency Timer and Class Cache Line Size Register Description ........................................................... 28
Table 9. Header Type and BIST Register Description .......................................................................................... 28
Table 10. OHCI Base Address Register Description ............................................................................................. 29
Table 11. CardBus Base Address Register Description ........................................................................................ 30
Table 12. PCI Subsystem Identification Register Description ............................................................................... 31
Table 13. Interrupt Line and Pin Register Description ........................................................................................... 32
Table 14. MIN_GNT and MAX_LAT Register Description ..................................................................................... 32
Table 15. PCI OHCI Control Register Description ................................................................................................. 33
Table 16. Capability ID and Next Item Pointer Register Description ..................................................................... 33
Table 17. Power Management Capabilities Register Description ......................................................................... 34
Table 18. Power Management Control and Status Register Description .............................................................. 35
Table 19 Power Management Data Register Description ..................................................................................... 36
Table 20. OHCI Register Map ............................................................................................................................... 37
Table 21. OHCI Version Register Description ....................................................................................................... 40
Table 22. GUID ROM Register Description ........................................................................................................... 41
Table 23. Asynchronous Transmit Retries Register Description ........................................................................... 41
Table 24. CSR Data Register Description ............................................................................................................. 42
Table 25. CSR Compare Register Description ...................................................................................................... 42
Table 26. CSR Control Register Description ........................................................................................................ 42
Table 27. Configuration ROM Header Register Description ................................................................................. 43
Table 28. Bus Identification Register Description .................................................................................................. 44
Table 29. Bus Options Register Description .......................................................................................................... 44
Table 30. GUID High Register Description ............................................................................................................ 45
Table 31. GUID Low Register Description ............................................................................................................. 45
Table 32. Configuration ROM Mapping Register Description ................................................................................ 46
Table 33. Posted Write Address Low Register Description ................................................................................... 47
Table 34. Posted Write Address High Register Description .................................................................................. 47
Table 35. Vendor ID Register Description ............................................................................................................. 47
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Table of Contents
(continued)
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.
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