xe1205 Semtech Corporation, xe1205 Datasheet - Page 10

• Manufacturer Part Number: xe1205
• Description: Low-power, High Link Budget Integrated Uhf Transceiver
• Manufacturer: Semtech Corporation

5.2.3.2
The raw output signal from the demodulator may contain jitter and glitches. The bit synchronizer converts the data output
of the demodulator into a glitch-free bit-stream DATA and generates a synchronized clock DCLK to be used for sampling
the DATA output (see below). DCLK is available on pin IRQ_1 when the chip operates in continuous mode.
To ensure the correct operation of the bit synchronizer, in addition to the requirement for the modulation index defined in
Section 5.2.3.1, the following conditions have to be satisfied:
The bit synchronizer is enabled by default. It is controlled by RXParam_Disable_bitsync. If the bit synchroniser is
disabled the output of the demodulator is directed to DATA and the DCLK output (IRQ_1 Pin in continuous mode) is set
to
The received bit rate is defined by the value of the MCParam_Br(6:0) configuration register, and is calculated as follows:
Bit rate =
For the Konnex standard operation, the bit rate is fixed at 32.768 kbit/s. The bit synchronizer is automatically configured
with the right bit rate value if the MCParam_Knx configuration bit is set high.
If needed, it is possible to select intermediate bit rates by changing the Over-Sampling Ratio (OSR) of the bit
synchronizer, whose default value is 32. The latter can be superseded by setting high the register TParam_Chg_OSR. In
this case, the bit rate becomes:
Bit rate =
where OSR(7:0) is the content of the register; TParam_OSR(7:0) as described in section 7.2.8.
For a correct operation of the bit synchronizer, the value of this register must be higher or equal to 15 and
(int(OSR)+1) * Bit_rate should be inferior or equal to 4.87MHz.
5.2.3.3
In receive mode this feature is activated by setting the RXParam_Pattern configuration register bit to high. The
demodulated signal is compared with a pattern stored in the Reg_pattern(31:0) registers. The PATTERN signal (mapped
to output pin IRQ_0) is driven by the output of this comparator and is synchronized by DCLK. It is set to high when a
matching condition is detected, otherwise set to low. PATTERN output is updated at the rising edge of DCLK. The
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DATA (NRZ)
·
·
·
·
DCLK
.
A preamble of 24 bits is required for synchronization
The preamble must be a sequence of
The bit stream must have at least one transition from
transmission
The bit rate accuracy must be better than ±5% (3% for Konnex mode operation)
Bit synchronizer in continuous mode
Pattern recognition block in continuous mode
int(Br(6
int(Br(6
152
152
.
.
34
34
:
:
0))
e
0))
e
3
3
+
+
1
1
where int(x) is the integer value of the unsigned binary representation of x.
×
int(
OSR
32
7 (
0 :
))
Figure 3: Bit synchronizer timing diagram
+
1
,
and
sent alternatively
10
to
or from
to
every 8 bits during data
XE1205
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