am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 10

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

Data Path
The transmit and receive data path illustrated in Figure 2
is identical for both channels. The receiver has three
8-bit buffer registers in a FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme creates
additional time for the CPU to service an interrupt at the
beginning of a block of high-speed data. Incoming data
are routed through one of several paths (data or CRC)
depending on the selected mode (the character length
in asynchronous modes also determines the data path).
10
Read Register Functions
Write Register Functions
RR0
RR1
RR2
RR3
RR6
RR7
RR8
RR10
RR12
RR13
RR15
AMD
Transmit/Receive buffer status and External
status
Special Receive Condition status
(also 10
WR15 bit D
Modified interrupt vector
(Channel B only)
Unmodified interrupt vector
(Channel A only)
Interrupt Pending bits
(Channel A only)
LSB Byte Count (14-bit counter)
(if WR15 bit D
MSB Byte Count (14-bit counter)
and 10
Receive buffer
Miscellaneous XMTR, RCVR status
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
External/Status interrupt information
19 bit FIFO Status (if WR15 bit D
19 bit FIFO Frame Reception Status if
2
is set)
2
set)
Table 1. Read and Write Register Functions
2
is set)
Am85C30
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR7
WR8
WR9
WR10
WR11
WR12
WR13
WR14
WR15
The transmitter has an 8-bit transmit data buffer register
loaded from the internal data bus and a 20-bit transmit
shift register that can be loaded either from the sync-
character registers or from the transmit data register.
Depending on the operational mode, outgoing data are
routed through one of four main paths before they are
transmitted from the Transmit Data output (TxD).
Write Register Functions
Command Register, Register Pointers CRC
initialize, initialization commands for the various
modes, shift right/shift left command
Interrupt conditions and data transfer mode
definition
Interrupt vector (accessed through either channel)
Receive parameters and control
Transmit/Receive miscellaneous parameters and
modes
Transmit parameters and controls
Sync character or SDLC address field
Sync character or SDLC flag
SDLC/HDLC enhancements (if bit D
set)
Transmit buffer
Master interrupt control and reset (accessed
through either channel)
Miscellaneous transmitter/receiver control bits,
data encoding
Clock mode control, Rx and Tx clock source
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
Miscellaneous control bits, DPLL control
External/Status interrupt control
0
of WR15 is