am41lv3204m Meet Spansion Inc., am41lv3204m Datasheet - Page 16

• Manufacturer Part Number: am41lv3204m
• Description: Stacked Multi-chip Package Mcp 32 Mbit 4 M ? 8 Bit/2 M ? 16-bit Flash Memory And 4 Mbit 512k ? 8-bit/256 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

(Note that this is a more restricted voltage range than
V
within V
mode, but the standby current will be greater. The de-
vice requires standard access time (t
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
June 10, 2003
IH
.) If CE#f and RESET# are held at V
CC
± 0.3 V, the device will be in the standby
DC Characteristics
DC Characteristics
table for the automatic
table for the standby
CE
) for read ac-
P R E L I M I N A R Y
IH
, but not
ACC
Am41LV3204M
+
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
IL
but not within V
AC Characteristics
SS
±0.3 V, the standby current will
IH
, output from the device is
CC4
tables for RESET# pa-
SS
). If RESET# is held
±0.3 V, the device
RP
, the
15