k4t1g084qa-zce6 Samsung Semiconductor, Inc., k4t1g084qa-zce6 Datasheet - Page 26
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k4t1g084qa-zce6
Manufacturer Part Number
k4t1g084qa-zce6
Description
1gb A-die Ddr2 Sdram Specification
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4T1G084QA-ZCE6.pdf
(28 pages)
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29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
signal applied to the device under test.
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
ential data strobe crosspoint for a rising signal and V
1G A-die DDR2 SDRAM
tRPST end point
tHZ,tRPST end point = 2*T1-T2
tHZ
DQS
DQS
Differential Input waveform timing
T1
T2
IL(dc)
tDS
<Test method for tLZ, tHZ, tRPRE and tRPST>
VOH + x mV
VOH + 2x mV
VOL + 2x mV
VOL + x mV
to the differential data strobe crosspoint for a falling signal applied to the device under test.
tDH
Page 26 of 28
VTT + 2x mV
VTT + x mV
VTT - x mV
VTT - 2x mV
tDS
tLZ,tRPRE begin point = 2*T1-T2
tDH
IL(ac)
level to the differential data strobe crosspoint for a falling
T1
T2
V
V
V
V
V
V
V
tLZ
tRPRE begin point
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
max
max
min
min
DDR2 SDRAM
Rev. 1.1 Aug. 2005
IH(ac)
IH(dc)
level to the differ-
level to the differ-