k4t51043qe-zlcc Samsung Semiconductor, Inc., k4t51043qe-zlcc Datasheet
k4t51043qe-zlcc
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... K4T51043QE K4T51083QE K4T51163QE 512Mb E-die DDR2 SDRAM Specification 60FBGA & 84FBGA with Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4T51043QE K4T51083QE K4T51163QE Table of Contents 1.0 Ordering Information ....................................................................................................................4 2.0 Key Features .................................................................................................................................4 3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5 3.1 x4 package pinout (Top View) : 60ball FBGA Package 3.2 x8 package pinout (Top View) : 60ball FBGA Package 3.3 x16 package pinout (Top View) : 84ball FBGA Package 3.4 FBGA Package Dimension(x4/x8) 3.5 FBGA Package Dimension(x16) 4 ...
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... K4T51043QE K4T51083QE K4T51163QE Revision History Revision Month Year 1.0 March 2006 - Initial Release 1.1 August 2006 - Revised the IDD values 1.2 September 2006 - Revised the IDD values 1.3 September 2006 - Added DDR2-800 CL6 - Added the detailed explanation on the notes for AC parameters 1.4 October 2006 - Corrected Typo 1 ...
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... All of Lead-free products are compliant for RoHS Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram” DDR2-667 5-5-5 K4T51043QE-ZC(L)E6 K4T51043QE-ZC(L)D5 K4T51043QE-ZC(L)CC K4T51083QE-ZC(L)E6 K4T51083QE-ZC(L)D5 K4T51083QE-ZC(L)CC K4T51163QE-ZC(L)E6 K4T51163QE-ZC(L)D5 K4T51163QE-ZC(L)CC ...
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... K4T51043QE K4T51083QE K4T51163QE 3.0 Package Pinout/Mechanical Dimension & Addressing Ball Locations (x4) 3.1 x4 package pinout (Top View) : 60ball FBGA Package VDD NC VSS A VSSQ NC DQS VSSQ DM B VDDQ VDDQ VDDQ DQ1 C VSSQ NC DQ3 DQ2 D VDDL VREF VSSDL VSS E CKE WE RAS F NC BA0 ...
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... K4T51043QE K4T51083QE K4T51163QE 3.2 x8 package pinout (Top View) : 60ball FBGA Package Ball Locations (x8 NU/ VSSQ VDD VSS A RDQS DM/ DQ6 VSSQ B DQS RDQS VDDQ DQ1 VDDQ C VDDQ DQ3 DQ4 DQ2 VSSQ D VDDL VSS VREF VSSDL E CKE WE F RAS NC BA0 BA1 G CAS ...
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... K4T51043QE K4T51083QE K4T51163QE 3.3 x16 package pinout (Top View) : 84ball FBGA Package 1 VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Note : 1. VDDL and VSSDL are power and ground for the DLL case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used. ...
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... K4T51043QE K4T51083QE K4T51163QE (Datum A) (Datum B) 60-∅0.45 Solder ball (Post reflow 0.50 ± 0.05) 3.4 FBGA Package Dimension(x4/x8) 9.00 ± 0.10 0. 6.40 3.20 0.80 1. (0.95) MOLDING AREA (1.90) 0 Bottom 9.00 ± 0.10 #A1 0.35 ± 0.05 Top 1.10 ± 0. DDR2 SDRAM INDEX MARK B Rev ...
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... K4T51043QE K4T51083QE K4T51163QE (Datum A) (Datum B) (Post reflow 0.50 ± 0.05) 3.5 FBGA Package Dimension(x16) 9.00 ± 0.10 0. 6.40 3.20 0.80 1. (0.95) 84-∅0.45 Solder ball (1.90) 0 Bottom 9.00 ± 0.10 #A1 0.35 ± 0.05 1.10 ± 0.10 Top DDR2 SDRAM INDEX MARK B 1 MOLDING AREA ...
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... K4T51043QE K4T51083QE K4T51163QE 4.0 Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the CK, CK Input positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing) ...
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... K4T51043QE K4T51083QE K4T51163QE 5.0 DDR2 SDRAM Addressing 512Mb Configuration # of Banks Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Banks Bank Address Auto precharge Row Address Column Address 1Gb ...
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... K4T51043QE K4T51083QE K4T51163QE 6.0 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on any pin relative IN, OUT T Storage Temperature STG Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... K4T51043QE K4T51083QE K4T51163QE 7.2 Operating Temperature Condition Symbol TOPER Operating Temperature Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate ...
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... K4T51043QE K4T51083QE K4T51163QE 7.6 Differential input AC logic Level Symbol Parameter V AC differential input voltage ID(AC differential cross point voltage IX(AC) Note : 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS) ...
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... K4T51043QE K4T51083QE K4T51163QE 9.0 OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications (0°C ≤ T ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V) CASE 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V ...
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... K4T51043QE K4T51083QE K4T51163QE 10.0 IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; IDD0 Address bus inputs are SWITCHING ...
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... K4T51043QE K4T51083QE K4T51163QE Note : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11 ...
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... CF7 IDD0 95 IDD1 115 IDD2P 8 5 IDD2Q 35 IDD2N 40 IDD3P-F 30 IDD3P-S 12 IDD3N 60 IDD4W 135 IDD4R 190 IDD5 115 IDD6 8 4 IDD7 280 128Mx4 (K4T51043QE) 800@CL=6 667@CL=5 533@CL=4 LF7 CE6 LE6 CD5 120 105 ...
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... K4T51043QE K4T51083QE K4T51163QE 12.0 Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 (0 ° ...
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... K4T51043QE K4T51083QE K4T51163QE 13.3 Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & ...
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... K4T51043QE K4T51083QE K4T51163QE Parameter Active to active command period for 2KB page size products Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time ...
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... K4T51043QE K4T51083QE K4T51163QE 14.0 General notes, which may apply for all AC parameters 1. DDR2 SDRAM AC timing reference load Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise repre sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment ...
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... K4T51043QE K4T51083QE K4T51163QE 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen- dent ...
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... K4T51043QE K4T51083QE K4T51163QE 15.0 Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...
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... K4T51043QE K4T51083QE K4T51163QE Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe ∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns ∆tDS ∆tDH ∆tDS ∆tDH 2.0 188 188 167 146 1.5 146 167 125 125 1 ...
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... K4T51043QE K4T51083QE K4T51163QE DQS DQS V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Setup Slew Rate Falling Signal Figure 5 - IIIustration of nominal slew rate for tDS (differential DQS,DQS) tDH tDS VREF to ac region nominal slew rate tVAC ∆TF ∆ Vil(ac)max Setup Slew Rate ...
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... K4T51043QE K4T51083QE K4T51163QE V DDQ V DQS IH(ac) V IH(dc) Note1 V REF(dc) V IL(dc) V IL(ac DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Setup Slew Rate Falling Signal Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS) ...
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... K4T51043QE K4T51083QE K4T51163QE DQS DQS V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac) nominal line V SS Setup Slew Rate Falling Signal Figure 7 - IIIustration of tangent line for tDS (differential DQS, DQS) tDS tDH nominal line REF region tangent line ∆TR tangent line[Vih(ac)min - V ...
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... K4T51043QE K4T51083QE K4T51163QE V DDQ V DQS IH(ac) V IH(dc) Note1 V REF(dc) V IL(dc) V IL(ac DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac) nominal line V SS Setup Slew Rate Falling Signal Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. Figure 8 - IIIustration of tangent line for tDS (single-ended DQS) ...
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... K4T51043QE K4T51083QE K4T51163QE DQS DQS V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Hold Slew Rate Rising Signal Figure 9 - IIIustration of nominal slew rate for tDH (differential DQS, DQS) tDH tDS REF region nominal REF slew rate region ∆ Vil(dc)max ...
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... K4T51043QE K4T51083QE K4T51163QE V DDQ V DQS IH(ac) V IH(dc) Note1 V REF(dc) V IL(dc) V IL(ac DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Hold Slew Rate Rising Signal Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. Figure 10 - IIIustration of nominal slew rate for tDH (single-ended DQS) ...
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... K4T51043QE K4T51083QE K4T51163QE DQS DQS V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Hold Slew Rate tangent line [ V Rising Signal Figure 11 - IIIustration of tangent line for tDH (differential DQS, DQS) tDH tDS REF region tangent line REF region nominal line ∆TR ...
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... K4T51043QE K4T51083QE K4T51163QE V DDQ V DQS IH(ac) V IH(dc) Note1 V REF(dc) V IL(dc) V IL(ac DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Hold Slew Rate Rising Signal Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. Figure 12 - IIIustration of tangent line for tDH (single-ended DQS) min ...
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... K4T51043QE K4T51083QE K4T51163QE 9. tIS and tIH (input setup and hold) derating Table 4 - Derating values for DDR2-400, DDR2-533 2.0 V/ns ∆tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ 0.8 -25 Address Slew 0.7 -43 rate(V/ns) 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 0.1 -1450 ∆tIS, ∆tIH Derating Values for DDR2-400, DDR2-533 CK, CK Differential Slew Rate 1 ...
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... K4T51043QE K4T51083QE K4T51163QE Table 5 - Derating values for DDR2-667, DDR2-800 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Command/ 0.8 -13 Address Slew 0.7 -22 rate(V/ns) 0.6 -34 0.5 -60 0.4 -100 0.3 -168 0.25 -200 0.2 -325 0.15 -517 0.1 -1000 For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS and ∆ ...
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... K4T51043QE K4T51083QE K4T51163QE DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Setup Slew Rate Falling Signal Figure 13 - IIIustration of nominal slew rate for tIS tIH tIS VREF to ac region nominal slew rate ∆TF ∆ Vil(ac)max Setup Slew Rate REF(dc) = Rising Signal ∆ ...
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... K4T51043QE K4T51083QE K4T51163QE DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac) nominal line V SS Setup Slew Rate Falling Signal Figure 14 - IIIustration of tangent line for tIS tIH tIS nominal line REF region tangent line ∆TR tangent line[Vih(ac)min - V Setup Slew Rate = Rising Signal ∆ ...
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... K4T51043QE K4T51083QE K4T51163QE DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Hold Slew Rate Rising Signal tIH tIS REF region nominal REF slew rate region ∆ Vil(dc)max REF(dc) Hold Slew Rate = ∆TR Falling Signal Figure 15 - IIIustration of nominal slew rate for tIH ...
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... K4T51043QE K4T51083QE K4T51163QE DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Hold Slew Rate Rising Signal tIH tIS REF region tangent line REF region nominal line ∆TR tangent line [ V - Vil(dc)max ] REF(dc) = ∆TR tangent line [ Vih(dc)min - V Hold Slew Rate ...
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... K4T51043QE K4T51083QE K4T51163QE 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
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... K4T51043QE K4T51083QE K4T51163QE 20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test ...
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... K4T51043QE K4T51083QE K4T51163QE 24. tWTR is at lease two clocks (2 x tCK nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test ...
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... K4T51043QE K4T51083QE K4T51163QE Definitions : - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. N ∑ tCK(avg) = tCK 200 where - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. N ∑ ...
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... K4T51043QE K4T51083QE K4T51163QE 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) ...
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... K4T51043QE K4T51083QE K4T51163QE 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have ...