k4t51043qe-zlcc Samsung Semiconductor, Inc., k4t51043qe-zlcc Datasheet - Page 29
k4t51043qe-zlcc
Manufacturer Part Number
k4t51043qe-zlcc
Description
512mb E-die Ddr2 Sdram Specification
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4T51043QE-ZLCC.pdf
(45 pages)
- Current page: 29 of 45
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K4T51043QE
K4T51083QE
K4T51163QE
DQS
Note1
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
V
V
V
V
V
V
Setup Slew Rate
IL(dc)
IL(ac)
DDQ
REF(dc)
IH(ac)
IH(dc)
Falling Signal
Figure 8 - IIIustration of tangent line for tDS (single-ended DQS)
max
max
V
V
V
V
V
V
V
min
min
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
nominal
SS
line
V
max
max
min
min
region
REF
=
tangent line[V
to ac
∆TF
∆TF
tDS
tangent
REF(dc)
line
29 of 45
Setup Slew Rate
- Vil(ac)max]
Rising Signal
tDH
nominal
line
=
∆TR
tangent line[Vih(ac)min - V
tDS
tangent
line
∆TR
tDH
V
REF
region
to ac
REF(dc)
]
DDR2 SDRAM
Rev. 1.8 July 2007
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