k4t56163qi Samsung Semiconductor, Inc., k4t56163qi Datasheet - Page 20

• Manufacturer Part Number: k4t56163qi
• Description: 256mb I-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4T56163QI
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS
through a 20 Ω to 10 kΩ resistor to insure proper operation.
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
They may be guaranteed by device design or tester correlation.
specifications and device operation are guaranteed for the full voltage range specified.
DQS/
DQS
DQ
DM
CK/CK
DQS/DQS
DQ
CK
CK
DQS
DQS
t
CH
Figure 3 - Data Input (Write) Timing
t
Figure 4 - Data Output (Read) Timing
RPRE
t
WPRE
DQS
DQS
t
V
t
V
CL
DQSQmax
IH
IL
(ac)
(ac)
t
DMin
DS
D
20 of 42
t
DQSH
t
QH
Q
V
V
IH
IL
(ac)
(ac)
t
DMin
DS
D
t
DQSL
Q
DMin
D
t
DH
V
t
V
DQSQmax
IH
IL
(dc)
(dc)
Q
DMin
D
t
DH
t
t
RPST
QH
V
Q
V
IH
IL
t
(dc)
WPST
(dc)
Rev. 1.0 October 2007
DDR2 SDRAM