k4s511632d-ul75 Samsung Semiconductor, Inc., k4s511632d-ul75 Datasheet - Page 12

• Manufacturer Part Number: k4s511632d-ul75
• Description: 512mb D-die Sdram
• Manufacturer: Samsung Semiconductor, Inc.

SDRAM 512Mb D-die (x4, x8, x16)
Notes :
14.0 AC Operating Test Conditions
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
15.0 Operating AC Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
(Fig. 1) DC output load circuit
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
and then rounding off to the next higher integer.
870Ω
Parameter
Parameter
3.3V
1200Ω
50pF
CAS latency = 3
CAS latency = 2
V
V
OH
OL
t
t
t
t
t
t
t
t
t
RAS
(DC) = 0.4V, I
(DC) = 2.4V, I
Symbol
RRD
RCD
t
RAS
t
CCD
RDL
DAL
CDL
BDL
RP
RC
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
OL
OH
= 2mA
= -2mA
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
Output
2 CLK + tRP
Version
(AC operating conditions unless otherwise noted)
100
75
15
20
20
45
65
2
1
1
1
2
1
(Fig. 2) AC output load circuit
Rev. 1.0 November. 2005
(V
Z0 = 50Ω
DD
= 3.3V ± 0.3V, T
CMOS SDRAM
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ns
ea
Vtt = 1.4V
Unit
50Ω
A
ns
50pF
V
V
V
= 0 to 70°C)
Note
2, 5
1
1
1
1
1
5
2
2
3
4