ic42s16400a ETC-unknow, ic42s16400a Datasheet

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... IC42S16400A Document Title 1M x 16Bit x 4 Banks (64-MBIT) SDRAM Revision History Revision No History 0A Initial Draft The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...

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... ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 DESCRIPTION The IC42S16400A are high-speed 67,108,864-bit syn- chronous dynamic random-access memories, orga- nized as 1,048,576 (word x bit x bank), respectively. ...

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... IC42S16400A 60-BALL VF-BGA ( 64M SDRAM ) 7 A10 VDD BA0 BA1 A11 VSS PIN DESCRIPTIONS A0 - A11 Address BA0,BA1 Bank Address DQ0 - DQ15 Data Input/Output CLK Clock CKE Clock Enable CS Chip Select RAS Row Address Strobe ...

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... IC42S16400A FUNCTIONAL BLOCK DIAGRAM CLK Clock Generator CKE Address Mode Register CS RAS CAS WE 4 Bank D Row Bank C Address Bank B Buffer & Refresh Counter Bank A Sense Amplifier Column Decoder & Column Latch Circuit Address Buffer & Burst Data Control Circuit Counter DQM DQ Integrated Circuit Solution Inc ...

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... IC42S16400A ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Supply Voltage (with respect Supply Voltage for Output (with respect to V DDQ V Input Voltage (with respect Output Voltage O I Short circuit output current O P Power Dissipation ( D T Operating Temperature OPT T Storage Temperature ...

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... IC42S16400A DC ELECTRICAL CHARACTERISTICS ( 70° 3.3 ± 0.3V DDQ Symbol Parameter I Operating Current ( Precharge Standby Current CC (In Power-Down Mode) I 2PS Precharge Standby Current (2) CC (In Non Power-Down Mode) I 2NS Active Standby Current CC (In Power-Down Mode) I 3PS ...

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... IC42S16400A AC TEST CONDITIONS ( 70° 3.3 ± 0.3V DDQ Parameter AC input Levels ( Input timing reference level /Output timing reference level Input rise and fall time Output load condition Output Load Conditions V V DDQ DDQ V OUT Device Under Test Integrated Circuit Solution Inc ...

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... IC42S16400A AC ELECTRICAL CHARACTERISTICS ( 70° 3.3 ± 0.3V DDQ Symbol Parameter t 3 CLK Cycle Time CLK to valid output delay ( CLK high pulse width CH t CLK low pulse width CL t CKE setup time CKE t CKE hold time ...

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... IC42S16400A Basic Features and Function Description Simplified State Diagram Mode Register Set Write (Write recovery) CKE WRITE WRITE SUSPEND CKE Write with Auto Precharge WRITE A CKE WRITE A SUSPEND CKE Precharge POWER ON Integrated Circuit Solution Inc. DR039-0A 02/19/2004 MRS REF IDLE CKE ...

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... IC42S16400A COMMAND TRUTH TABLE Symbol Command DESL Device deselect NOP No operation MRS Mode register set ACT Bank activate READ Read READA Read with auto precharge WRIT Write WRITA Write with auto precharge PRE Precharge select bank PALL Precharge all banks BST ...

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... IC42S16400A OPERATION COMMAND TABLE Current State Command Idle DESL NOP or BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Active DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL ...

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... IC42S16400A OPERATION COMMAND TABLE Current State Command DESL Write with auto NOP precharge BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Precharging NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Row activating NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF ...

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... IC42S16400A OPERATION COMMAND TABLE Current State Command DESL Write NOP recovering BST with auto READ/READA precharge WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Auto NOP/BST Refreshing READ/WRIT ACT/PRE/PALL REF/SELF/MRS Mode DESL register NOP setting BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle. ...

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... IC42S16400A CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK (n - 1)would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t RC Idle After t RC Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...

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... IC42S16400A Initiallization Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs. 2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us. ...

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... IC42S16400A MODE REGISTER LTMODE WT JEDEC Standard Test Set Burst Read and Burst Write X = Don’t care Bits2 - 000 ...

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... IC42S16400A Burst Length and Sequence Burst of Two Starting Address (column address A0, binary Burst of Four Starting Address (column address A1 - A0, binary Burst of Eight Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Integrated Circuit Solution Inc. ...

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... IC42S16400A Address Bits of Bank-Select and Precharge A10 A11 A12 A13 Row (Activate command A10 A11 A12 A13 Row (Precharge command A10 A11 A12 A13 Co1. (CAS strobes) ...

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... IC42S16400A Precharge The precharge command can be asserted anytime after t Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after t (min.) is satisfied. The parameter t RP The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows ...

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... IC42S16400A Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. In the write cycle, t (min.) must be satisfied before asserting the next activate command to the bank being precharged. ...

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... IC42S16400A Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of t input to the device. WRITE with AUTO PRECHRGE T0 CLK Command CAS latency = 2 DQ Command CAS latency = 3 DQ Remark WRITA means WRITE with AUTO Precharge In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference ...

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... IC42S16400A Read / Write Command Interval Read to Read Command Interval During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction. ...

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... IC42S16400A Write to Read Command Interval The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first D WRITE to READ Command Interval T0 CLK ...

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... IC42S16400A READ to WRITE Command Interval T0 CLK Command DQM DQ Hi CLK Command Read DQM DQ T0 CLK Command DQM Read Write cycle Read Q2 necessary CAS latency Burst length=8, CAS latency ...

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... IC42S16400A BURST Termination There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command. BURST Stop Command During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command ...

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... IC42S16400A PRECHARGE TERMINATION PRECHARGE TERMINATION in READ Cycle During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after t When CAS latency is 2, the read data will remain valid until one clock after the precharge command. ...

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... IC42S16400A Precharge Termination in WRITE Cycle During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after t invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command ...

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... IC42S16400A Mode Register Set T0 T1 CLK CKE CS RAS CAS WE BS0,1 A10 ADD DQM Hi-Z DQ Precharge Command All Banks RSC Address Key t RP Mode Register Command Set Command T10 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 ...

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... IC42S16400A AC Parameters for Write Timing ( CLK CK2 CH t CKE CMS t CKS t CMH CS RAS CAS WE *BS0 A10 ADD DQM t RCD DQ t RRD QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 ...

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... IC42S16400A AC Parameters for Write Timing ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CLK CK3 t CMS t CKE CKS t CMH CS RAS CAS WE *BS0 A10 ADD DQM ...

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... IC42S16400A AC Parameters for Read Timing ( CLK CK2 CKE t CKS CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ Activate Command Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 CMS t CMH ...

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... IC42S16400A AC Parameters for Read Timing ( CLK CK3 t CKE CMS t CKS CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ Activate Command Bank A BS1=”L”, Bank C,D = Idle CMH t RRD t RAS AC3 t AC3 ...

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... IC42S16400A Power on Sequence and Auto Refresh (CBR CLK High level CKE is required CS RAS CAS WE BS0, 1 A10 ADD DQM High Level is Necessary t RP Hi-Z DQ Precharge 1st Auto Command Refresh Inputs All Banks Command must be stable for 200us Integrated Circuit Solution Inc. ...

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... IC42S16400A Clock Suspension During Burst Read (Using CKE CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ Read Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Clock Suspension During Burst Read (Using CKE CLK t CK3 CKE CS RAS CAS WE *BS0 RAa A10 ADD RAa CAa DQM Hi-Z DQ Activate Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 ...

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... IC42S16400A Clock Suspension During Burst Write (Using CKE CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ DAa0 Clock Activate Suspended Command 1 Cycle Bank A Write Command Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Clock Suspension During Burst Write (Using CKE CLK t CK3 CKE CS RAS CAS WE *BS0 RAa A10 ADD RAa CAa DQM Hi-Z DQ DAa0 Activate Suspended Command Bank A Write Command Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. ...

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... IC42S16400A Power Down Mode and Clock Mask CLK t CK2 t CKS CKE CS RAS CAS WE *BS0 A10 RAa RAa ADD RAa DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A Power Down Power Down Mode Entry Mode Exit BS1=”L”, Bank C,D = Idle ...

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... IC42S16400A Auto Refresh (CBR CLK t CK2 CKE CS RAS CAS WE *BS0, 1 A10 ADD DQM t RP Hi-Z DQ Precharge CBR Refresh Command Command All Banks BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Self Refresh (Entry and Exit CLK CKE CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ All Banks Self refresh must be idle Entry BS1=”L”, Bank C,D = Idle Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High ...

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... IC42S16400A Random Column Read (Page With Same Bank CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD CAa RAa DQM Hi-Z DQ Precharge Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 ...

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... IC42S16400A Random Column Read (Page With Same Bank CLK t CK3 CKE CS RAS CAS WE *BS0 A10 RAa ADD CAa RAa DQM Hi-Z DQ Activate Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Random Column Write (Page With Same Bank CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra ADD Ra Ca DQM Hi-Z DQ Da0 Da1 Write Activate Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 ...

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... IC42S16400A Random Column Write (Page With Same Bank CLK t CK CKE CS RAS CAS WE *BS0 A10 Ra ADD Ca Ra DQM Hi-Z DQ Da0 Activate Write Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Random Row Read (Interleaving Banks CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 ADD t t AC2 RCD DQM Hi-Z DQ QBa0 Activate Read Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 ...

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... IC42S16400A Random Row Read (Interleaving Banks CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 ADD t RCD DQM Hi-Z DQ Read Activate Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Random Row Write (Interleaving Banks CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 ADD t DQM RCD Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 Activate Write Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc ...

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... IC42S16400A Random Row Write (Interleaving Banks CLK t CK CKE High CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 Write Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Read and Write Cycle ( CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ Write Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Read and Write Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 RAa ADD CAa RAa DQM Hi-Z DQ Activate Read Command Command Bank A Bank A BS1=” ...

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... IC42S16400A Interleaved Column Read Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra ADD DQM AC2 RCD Hi-Z DQ Activate Read Command Command ...

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... IC42S16400A Interleaved Column Read Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 Ra ADD Ca Ra DQM t RCD t RRD Hi-Z DQ Activate Read Command Command Bank A ...

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... IC42S16400A Interleaved Column Write Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra ADD RCD DQM t RRD Hi-Z DQ DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 ...

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... IC42S16400A Interleaved Column Write Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 Ra ADD RCD DQM t RRD Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...

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... IC42S16400A Auto Precharge after Read Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...

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... IC42S16400A Auto Precharge after Read Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ Activate Activate Command Command ...

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... IC42S16400A Auto Precharge after Write Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...

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... IC42S16400A Auto Precharge after Write Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...

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... IC42S16400A Full Page Read Cycle ( CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa Activate Activate Read Command Command Command Bank A Bank B Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. ...

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... IC42S16400A Full Page Read Cycle ( CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra ADD Ra Ca DQM Hi-Z DQ Activate Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Full Page Write Cycle ( CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa QAa+1 QAa+2 QAa+3 QAa-1 QAa Activate Write Activate Command Command Command Bank A Bank B Bank A The burst counter wraps ...

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... IC42S16400A Full Page Write Cycle ( CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra ADD Ra Ca DQM Hi-Z DQ DAa DAa+1 Activate Write Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Full Page Random Column Read CLK t CK2 CKE CS RAS CAS WE BS A10 Ra Ra ADD DQM Hi-Z DQ Activate Activate Command Command Bank A Bank B Read Command Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 ...

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... IC42S16400A Full Page Random Column Write CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 Activate Activate Command Command Bank A Bank B Write Command Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IC42S16400A Precharge Termination of a Burst ( CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ QAa0 QAa1 QAa2 Activate Write Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc ...

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... IC42S16400A Precharge Termination of a Burst ( CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa t DPL t DQM RCD Hi-Z DQ DAa0 DAa1 Precharge Activate Write Command Command Command Bank A Bank A Bank A Write Data is masked BS1=”L”, Bank C,D = Idle ...

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... IC42S16400A-7TG 400mil TSOP-2(Pb-free) IC42S16400A-7BG 60Ball VF-BGA(Pb-free) Order Part No. Package IC42S16400A-6TI 400mil TSOP-2 IC42S16400A-6TIG 400mil TSOP-2(Pb-free) IC42S16400A-6BIG 60Ball VF-BGA(Pb-free) IC42S16400A-7TI 400mil TSOP-2 IC42S16400A-7TIG 400mil TSOP-2(Pb-free) IC42S16400A-7BIG 60Ball VF-BGA(Pb-free) 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. ...