k4h1g0838m Samsung Semiconductor, Inc., k4h1g0838m Datasheet - Page 11

• Manufacturer Part Number: k4h1g0838m
• Description: 1gb M-die Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM 1Gb M-die (x4, x8)
Note :
1.These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
3. Unused pins are tied to ground.
4. This parameteer is sampled. For DDR266 and DDR333 VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +0.25V+0.2V. For
12.0 DDR SDRAM Spec Items & Test Conditions
13.0 Input/Output Capacitance
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Precharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
Vin = Vref for DQ,DQS and DM.
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for
DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing
once per clock cycle; Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and
other control inputs stable at >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for
DDR333, 5ns for DDR400; DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266(A2), CL=2.5 at
tCK=7.5ns for DDR266(B0), tCK=6ns for DDR333, CL=3 at tCK=5ns for DDR400; 50% of data changing on every
transfer; lout = 0 m A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2
at tCK=7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), 6ns for DDR333, 5ns for DDR400; DQ, DM
and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) which is 12*tCK for DDR200 at tCK=10ns; 16*tCK for DDR266 at
tCK=7.5ns; 20*tCK for DDR333 at tCK=6ns, 24*tCK for DDR400 at tCK=5ns; distributed refresh
Self refresh current; CKE =< 0.2V; External clock on; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for
DDR333, 5ns for DDR400.
Operating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
This is required to match signal propagation times of DQ, DQS, and DM in the system.
DDR400, VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V. For all devices, f=100MHz, tA=25°C, Vout(dc) = VDDQ/2, Vout(peak to
peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace
matching at the board level).
Input capacitance
(A0 ~ A13, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
Input capacitance( CK, CK )
Data & DQS input/output capacitance
Input capacitance(DM for x4/8, UDM/LDM for x16)
Parameter
Conditions
Symbol
COUT
CIN1
CIN2
CIN3
Min
2
2
4
4
Max
3
3
5
5
Rev. 1.1 June. 2005
Delta
0.25
0.5
0.5
DDR SDRAM
( T
A
= 25°C, f=100MHz)
Unit
pF
pF
pF
pF
Symbol
IDD4W
IDD2Q
IDD2P
IDD3P
IDD3N
IDD4R
IDD7A
IDD2F
IDD0
IDD1
IDD5
IDD6
1,2,3,4
1,2,3,4
Note
4
4