k4h1g0838m Samsung Semiconductor, Inc., k4h1g0838m Datasheet - Page 4

• Manufacturer Part Number: k4h1g0838m
• Description: 1gb M-die Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM 1Gb M-die (x4, x8)
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H1G0438M-TC/LB3
K4H1G0438M-TC/LA2
K4H1G0438M-TC/LB0
K4H1G0838M-TC/LB3
K4H1G0838M-TC/LA2
K4H1G0838M-TC/LB0
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Part No.
[DQS] (x4,x8) & [L(U)DQS] (x16)
B3(DDR333@CL=2.5)
256M x 4
128M x 8
Org.
133MHz
166MHz
2.5-3-3
-
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Max Freq.
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
-
Interface
SSTL2
Rev. 1.1 June. 2005
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
66pin TSOP II
-
Package