m464s0924dts Samsung Semiconductor, Inc., m464s0924dts Datasheet

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m464s0924dts

Manufacturer Part Number
m464s0924dts
Description
8mx64 Sdram Sodimm Based On 8mx16, 4banks, 4k Refresh, 3.3v Synchronous Drams With Spd
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
PIN CONFIGURATIONS (Front side/back side)
M464S0924DTS SDRAM SODIMM
8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
Dynamic RAM high density memory module. The Samsung
M464S0924DTS consists of four CMOS 8M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and
a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-
epoxy substrate. Three 0.1uF decoupling capacitors are
mounted on the printed circuit board in parallel for each
SDRAM. The M464S0924DTS is a Small Outline Dual In-line
Memory Module and is intended for mounting into 144-pin
edge connector sockets.
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Pin Front Pin
Synchronous design allows precise cycle control with the use
M464S0924DTS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1
3
5
7
9
The Samsung M464S0924DTS is a 8M bit x 64 Synchronous
DQM0
DQM1
DQ10
DQ11
DQ12
DQ13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
V
V
V
V
V
V
A0
A1
A2
SS
DD
SS
DD
SS
DD
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
DQM4
DQM5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
Back
V
V
V
V
V
V
A3
A4
A5
SS
DD
SS
DD
SS
DD
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
Voltage Key
Front
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
CLK0
*CS1
RAS
CS0
V
V
W E
V
V
V
NC
NC
DU
NC
NC
SS
DD
SS
DD
SS
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
*CKE1
*CLK1
DQ46
DQ47
CKE0
DQ48
DQ49
DQ50
DQ51
DQ52
Back
CAS
*A12
*A13
V
V
V
V
V
NC
NC
NC
NC
SS
DD
SS
DD
SS
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
95
97
99
A10/AP
DQM2
DQM3
**SDA
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Front
V
V
V
V
V
V
V
A6
A8
A9
DD
DD
DD
DD
SS
SS
SS
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
96
98
DQM6
DQM7
**SCL
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Back
FEATURE
• Performance range
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the
• Serial presence detect with EEPROM
• PCB : Height (1,000mil) , double sided component
BA0
BA1
V
V
A11
V
V
V
V
V
A7
M464S0924DTS-L7C/C7C
M464S0924DTS-L1H/C1H
DD
DD
DD
DD
M464S0924DTS-L7A/C7A
SS
SS
SS
M464S0924DTS-L1L/C1L
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
system clock
Part No.
PIN NAMES
*
** These pins should be NC in the system
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CLK0
CKE0
CS0
RAS
CAS
WE
DQM0 ~ 7
V
V
SDA
SCL
DU
NC
DD
SS
These pins are not used in this module.
Pin Name
which does not support SPD.
PC133/PC100 SODIMM
0.3V power supply
Rev. 0.1 Sept. 2001
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Clock enable input
Chip select input
Row address storbe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Serial data I/O
Serial clock
Don t use
No connection
133MHz (7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
Max Freq. (Speed)
Function

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