m464s0924dts Samsung Semiconductor, Inc., m464s0924dts Datasheet - Page 10

• Manufacturer Part Number: m464s0924dts
• Description: 8mx64 Sdram Sodimm Based On 8mx16, 4banks, 4k Refresh, 3.3v Synchronous Drams With Spd
• Manufacturer: Samsung Semiconductor, Inc.

M464S0924DTS-C7C/L7C/C7A/L7A/C1H/L1H/C1L/L1H
M464S0924DTS
Byte #
Organization : 8Mx64
Composition : 8Mx16 * 4
Used component part # : K4S281632D-TC7C/TL7C/TC75/TL75/TC1H/TL1H/TC1L/TL1L
# of rows in module : 1 Row
# of banks in component : 4 banks
Feature : 1,000mil height & double sided component
Refresh : 4K/64ms
Contents ;
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuraion type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time from clock @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock @CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
Row
Rows
density
on this assembly
Function Described
banks
RCD
RP
)
)
RAS
on SDRAM device
)
R RD
)
7.5ns
5.4ns
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
2 & 3
15ns
15ns
15ns
45ns
-7C
15.625us, support self refresh
precharge all, auto precharge
Non-buffered, non-registered
Burst Read Single bit Write
-
-
+/- 10% voltage tolerance,
& redundant addressing
Function Supported
1, 2, 4, 8 & full page
256bytes (2K-bit)
1
7.5ns
5.4ns
2 & 3
1.5ns
0.8ns
1.5ns
10ns
20ns
15ns
20ns
45ns
t
-7A
6ns
CCD
row
Non parity
128bytes
-
-
4
SDRAM
LVTTL
64 bits
0 CLK
0 CLK
1
None
banks
x16
1 2
row
= 1CLK
of 64MB
9
-
2 & 3
10ns
10ns
20ns
20ns
20ns
50ns
-1H
6ns
6ns
2ns
1ns
2ns
-
-
2 & 3
10ns
12ns
20ns
20ns
20ns
50ns
-1L
6ns
7ns
2ns
1ns
2ns
PC133/PC100 SODIMM
-
-
75h
54h
06h
75h
54h
00h
00h
0Fh
0Fh
0Fh
2Dh
15h
08h
15h
-7C
Rev. 0.1 Sept. 2001
75h
54h
06h
A0h
60h
00h
00h
14h
0Fh
14h
2Dh
15h
08h
15h
-7A
Hex value
0Ch
0Eh
80h
08h
04h
09h
01h
40h
00h
01h
00h
80h
10h
00h
01h
8Fh
04h
01h
01h
00h
10h
A0h
A0h
-1H
60h
06h
60h
00h
00h
14h
14h
14h
32h
20h
10h
20h
A0h
C0h
-1L
60h
06h
70h
00h
00h
14h
14h
14h
32h
20h
10h
20h
Note
1
1
2
2
2
2