m368l3223ctl Samsung Semiconductor, Inc., m368l3223ctl Datasheet - Page 3

• Manufacturer Part Number: m368l3223ctl
• Description: 256mb Ddr Sdram Module Unbuffered 184pin Dimm 64-bit Non-ecc/parity
• Manufacturer: Samsung Semiconductor, Inc.

M368L3223CTL
M368L3223CTL DDR SDRAM 184pin DIMM
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
PIN CONFIGURATIONS (Front side/back side)
GENERAL DESCRIPTION
Rate SDRAM high density memory modules. The Samsung
M368L3223CTL consists of eight CMOS 32M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M368L3223CTL
is Dual In-line Memory Modules and inten-ded for mounting
into 184pin edge connector sockets.
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
Pin Front Pin Front Pin
The Samsung M368L3223CTL is 32M bit x 64 Double Data
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
Synchronous design allows precise cycle control with the use
1
2
3
4
5
6
7
8
9
VDDQ
VDDQ
VDDQ
VREF
DQS0
DQS1
DQS2
DQ10
DQ11
CKE0
DQ16
DQ17
DQ18
DQ19
/CK1
DQ0
DQ1
DQ2
VDD
DQ3
DQ8
DQ9
VSS
VSS
CK1
VSS
VSS
NC
NC
A 9
A 7
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
KEY
*DQS8
VDDQ
DQS3
DQS4
DQ24
DQ25
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
*CB0
*CB1
*CB2
*CB3
VDD
VDD
VSS
VSS
VSS
BA1
VSS
BA0
A 5
A 4
A 2
A 1
A 0
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDID
Front
VDDQ
VDDQ
DQS5
DQS6
DQS7
DQ41
DQ42
DQ43
*/CS2
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
/CAS
VDD
/CK2
VDD
SDA
/WE
VSS
VSS
CK2
VSS
VSS
SCL
NC
Pin
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
9 3
9 4
9 5
9 6
9 7
9 8
9 9
*CKE1
VDDQ
VDDQ
VDDQ
Back
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
*BA2
VSS
DQ4
DQ5
DM0
DQ6
DQ7
VSS
DM1
VDD
VSS
DM2
VDD
A12
A11
NC
NC
NC
A8
184pin Unbuffered DDR SDRAM MODULE
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
KEY
VDDQ
VDDQ
VDDQ
Back
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
*DM8
*CB4
*CB5
/CK0
*CB6
*CB7
VSS
DM3
VSS
CK0
VSS
VSS
VDD
DM4
VSS
A10
A6
A3
• Performance range
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
•
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component
FEATURE
M368L3223CTL-C(L)B3 167MHz(6.0ns@CL=2.5)
M368L3223CTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L3223CTL-C(L)B0 133MHz(7.5ns@CL=2.5)
Double-data-rate architecture; two data transfers per clock cycle
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VDDSPD
Part No.
VDDQ
VDDQ
VDDQ
VDDQ
Back
DQ45
*/CS1
DQ46
DQ47
*/CS3
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
/RAS
/CS0
DM5
*A13
VDD
DM6
DM7
VSS
VSS
SA0
SA1
SA2
NC
PIN DESCRIPTION
*
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0, CK0 ~ CK2, CK2
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
These pins are not used in this module.
Pin Name
Max Freq.
Rev. 0.3 May. 2002
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
Function
Interface
SSTL_2