m368l3223ctl Samsung Semiconductor, Inc., m368l3223ctl Datasheet - Page 6

• Manufacturer Part Number: m368l3223ctl
• Description: 256mb Ddr Sdram Module Unbuffered 184pin Dimm 64-bit Non-ecc/parity
• Manufacturer: Samsung Semiconductor, Inc.

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
DDR SDRAM IDD spec table
AC OPERATING TEST CONDITIONS
M368L3223CTL
AC OPERATING CONDITIONS
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
IDD6
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Symbol
IDD4W
IDD2P
IDD2Q
IDD3P
IDD3N
IDD4R
IDD7A
IDD2F
IDD0
IDD1
IDD5
Low power
Normal
Parameter/Condition
IX
is expected to equal 0.5*V
B3(DDR333@CL=2.5)
Parameter
1120
1480
1400
1560
2800
920
240
160
320
480
24
24
12
DDQ
A2(DDR266@CL=2)
(V
184pin Unbuffered DDR SDRAM MODULE
of the transmitting device and must track variations in the DC level of the same.
DD
=2.5V, V
1240
1160
1440
2280
760
960
216
144
256
400
24
24
12
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
DDQ
=2.5V, T
VREF+0.31/VREF-0.31
See Load Circuit
0.5 * VDDQ
0.5*VDDQ-0.2
VREF + 0.31
Value
VREF
A
1.5
Vtt
= 0 to 70
Min
0.7
B0(DDR266@CL=2.5)
C
)
1240
1160
1440
2280
0.5*VDDQ+0.2
760
960
216
144
256
400
24
24
12
VREF - 0.31
VDDQ+0.6
Max
Rev. 0.3 May. 2002
Unit
V
V
V
V
V
Unit
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
Optional
Note
Notes
Note
3
3
1
2