m393t5663cza-cf7/e6 Samsung Semiconductor, Inc., m393t5663cza-cf7/e6 Datasheet - Page 4

• Manufacturer Part Number: m393t5663cza-cf7/e6
• Description: Ddr2 Registered Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

2.0 Features
RDIMM
1.0 DDR2 Registered DIMM Ordering Information
Note :
1. “Z” of Part number(11th digit) stand for Lead-free products. and "J" of Part number(11th digit) stand for dual-die package products.
2. “3” of Part number(12th digit) stand for Non-parity Register products. and "A" of Part number(12th digit) stand for Parity Register products.
3. "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products.
3.0 Address Configuration
M393T5663CZ3-CD5/CC
M393T5663CZA-CF7/E6
M393T5660CZ3-CD5/CC
M393T5660CZA-CF7/E6
M393T5160CZ3-CD5/CC
M393T5160CZA-CF7/E6
M392T5160CJA-CF7/E6
M393T1G60CJA-CE6/D5
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
• 200 MHz f
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of Lead-free products are compliant for RoHS
- support High Temperature Self-Refresh rate enable feature
DDQ
256Mx4(1Gb) based Module
128Mx8(1Gb) based Module
CL-tRCD-tRP
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
Part Number
= 1.8V ± 0.1V
CK
Organization
for 400Mb/sec/pin, 267MHz f
Density
F7(DDR2-800)
2GB
2GB
2GB
2GB
4GB
4GB
4GB
8GB
6-6-6
533
667
800
-
Organization
CK
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
Row Address
for 533Mb/sec/pin, 333MHz f
1Gx72
CASE
A0-A13
A0-A13
85qC, 3.9us at 85qC < T
E6(DDR2-667)
DDP512Mx4(K4T2G044QC)*18EA
DDP512Mx4(K4T1G044QC)*36EA
128Mx8(K4T1G084QC)*18EA
128Mx8(K4T1G084QC)*18EA
256Mx4(K4T1G044QC)*18EA
256Mx4(K4T1G044QC)*18EA
256Mx4(K4T1G044QC)*36EA
256Mx4(K4T1G044QC)*36EA
5-5-5
Component Composition
400
533
667
-
4 of 26
Column Address
A0-A9, A11
CK
CASE
A0-A9
for 667Mb/sec/pin, 400MHz f
< 95 qC
D5(DDR2-533)
4-4-4
400
533
-
-
Number of Rank
Bank Address
BA0-BA2
BA0-BA2
2
2
1
1
2
2
2
4
CK
Rev. 1.4 November 2007
for 800Mb/sec/pin
CC(DDR2-400)
3-3-3
400
400
DDR2 SDRAM
Parity Register
-
-
X
O
X
O
X
O
O
O
Auto Precharge
A10
A10
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
18.30mm
30.00mm
Mbps
Mbps
Mbps
Mbps
Unit
Height
CK