m470l3223dt0 Samsung Semiconductor, Inc., m470l3223dt0 Datasheet
m470l3223dt0
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m470l3223dt0 Summary of contents
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... M470L3223DT0 256MB DDR SDRAM MODULE (32Mx64 based on 32Mx 8 DDR SDRAM) 64bit Non-ECC/Parity 200pin SODIMM Revision 0.0 Dec. 2001 Rev. 0.0 Dec. 2001 ...
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... M470L3223DT0 Revision History Revision 0.0 (Dec. 2001) 1. First release. Rev. 0.0 Dec. 2001 ...
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... M470L3223DT0 200pin DDR SDRAM SODIMM 32Mx64 200pin DDR SDRAM SODIMM based on 32Mx8 GENERAL DESCRIPTION The Samsung M470L3223DT0 is 32M bit x 64 Double Data Rate SDRAM high density memory modules based on third gen of 256Mb DDR SDRAM respectively. The Samsung M470L3223DT0 consists of eight CMOS 32M x ...
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... M470L3223DT0 FUNCTIONAL BLOCK DIAGRAM S0 DQS0 DQS S DM0 DM DQ0 I/0 0 DQ1 I/0 1 DQ2 I DQ3 I/0 3 DQ4 I/0 4 DQ5 I/0 5 DQ6 I/0 6 DQ7 I/0 7 DQS1 DQS S DM1 DM DQ8 I/0 0 DQ9 I/0 1 DQ10 I DQ11 I/0 3 DQ12 I/0 4 DQ13 I/0 5 DQ14 I/0 6 DQ15 I/0 7 DQS2 DQS S DM2 DM DQ16 I/0 0 DQ17 I/0 1 DQ18 I DQ19 I/0 3 DQ20 I/0 4 DQ21 I/0 5 DQ22 I/0 6 DQ23 I/0 7 DQS3 ...
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... M470L3223DT0 Absolute Maximum Rate Parameter Voltage on any pin relative to V Voltage on V & V supply relative DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... M470L3223DT0 DDR SDRAM SPEC Items and Test Conditions Recommended operating conditions Unless Otherwise Noted, T Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition Percharge power-down standby current ...
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... M470L3223DT0 DDR SDRAM I spec table DD Symbol B3(DDR333@CL=2.5) IDD0 720 IDD1 960 IDD2P 24 IDD2F 200 IDD2Q 160 IDD3P 280 IDD3N 440 IDD4R 1360 IDD4W 1360 IDD5 1440 Normal 24 IDD6 Low power 12 IDD7A 2600 I * Module was calculated on the basis of component DD < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > ...
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... M470L3223DT0 DD7A I : Operating current: Four bank operation 1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 2. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read : repeat the same timing with random address changing *100% of data changing at every burst - DDR266B(133Mhz, CL=2 ...
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... M470L3223DT0 AC OPERATING TEST CONDITIONS Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output Input/Output CAPACITANCE Parameter Input capacitance Input capacitance(CKE ...
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... M470L3223DT0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2 ...
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... M470L3223DT0 Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command 64Mb, 128Mb Refresh interval time 256Mb Output DQS valid window ...
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... M470L3223DT0 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 This derating table is used to increase t based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 This derating table is used to increase t based on the lesser of AC-AC slew rate and DC-DC slew rate. ...
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... M470L3223DT0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2.0 Clock cycle time CL=2.5 Clock high level width ...
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... M470L3223DT0 Parameter Mode register set cycle time Control & Address input pulse width (for each input) DQ & DM input pulse width(for each input) Exit self refresh to non read command Exit self refresh to read command 64Mb, 128Mb Refresh interval time 256Mb Output DQS valid window ...
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... M470L3223DT0 Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...
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... M470L3223DT0 PACKAGE DIMENSIONS 0.16 0.039 (4.00 0.10) 1 0.086 0.456 2.15 11.40 0.07 (1.8) 0.098 2.45 2 0.150 Max (3.80 Max) 0.04 0.0039 (1.00 0.10) Tolerances : .006(.15) unless otherwise specified The used device is 32Mx8 SDRAM, TSOP SDRAM Part No. : K4H560838D-TC/L 2.70 (67.60) 2.50 (63.60 1.896 (47.40) 0.17 (4.20) 0.096 (2.40 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z Units : Inches (Millimeters) Full R 2x 199 2- 0.07 (1.80) Y 200 0.018 ...