m470l1714bt0 Samsung Semiconductor, Inc., m470l1714bt0 Datasheet - Page 11

• Manufacturer Part Number: m470l1714bt0
• Description: 128mb Ddr Sdram Module 16mx64 Based On 8mx16 Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Note : 1. Maximum burst refresh of 8
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
M470L1714BT0
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
4. A write command can be applied with t
5. For registered DINNs, t
but system performance (bus turnaround) will degrade accordingly.
period jitter due to crosstalk (t
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
Parameter
64Mb, 128Mb
256Mb
CL
and t
JIT
CH
(crosstalk)
Symbol
tWPST
tPDEX
tDIPW
are
tMRD
tXSW
tQHS
tXSA
tXSR
tREF
tDS
tDH
tQH
tHP
RCD
45% of the period including both the half period jitter (t
) on the DIMM.
satisfied after this command.
or tCHmin
-TCA2(DDR266A)
tHPmin
tCLmin
-tQHS
1.75
15.6
0.25
Min
200
0.5
0.5
7.8
15
10
95
75
Max
0.75
-
-
or tCHmin
-TCB0(DDR266B)
tHPmin
tCLmin
-tQHS
1.75
15.6
0.25
Min
200
0.5
0.5
7.8
200pin DDR SDRAM SODIMM
15
10
75
Max
0.75
-
-
or tCHmin
tHPmin
-TCA0 (DDR200)
tCLmin
-tQHS
15.6
0.25
Min
116
200
0.6
0.6
7.8
16
10
80
2
Rev. 0.1 June. 2001
JIT(HP)
) of the PLL and the half
Max
0.8
-
-
Cycle
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
us
us
ns
ns
ns
7,8,9
7,8,9
Note
4
1
1
5
3