m470l1714bt0 Samsung Semiconductor, Inc., m470l1714bt0 Datasheet - Page 8

• Manufacturer Part Number: m470l1714bt0
• Description: 128mb Ddr Sdram Module 16mx64 Based On 8mx16 Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
I
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
4. Timing patterns
M470L1714BT0
AC Operating Conditions
DD7A
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
changing. lout = 0mA
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
: Operating current: Four bank operation
Parameter/Condition
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
200pin DDR SDRAM SODIMM
Min
0.5*VDDQ+0.2
VREF - 0.31
VDDQ+0.6
Max
Rev. 0.1 June. 2001
Unit
V
V
V
V
Note
3
3
1
2