hys64t128021edl-25fb2 Qimonda, hys64t128021edl-25fb2 Datasheet - Page 19

• Manufacturer Part Number: hys64t128021edl-25fb2
• Description: 200-pin So-dimm Ddr2 Sdram Modules Ddr2 Sdram
• Manufacturer: Qimonda

26)
27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
28) 0 °C≤
29) 85 °C <
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
31)
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support
35)
36) This timing parameter is relaxed than Industry Standard
Rev. 1.20, 2008-06
08212006-PKYN-2H1B
t
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
and 95 °C.
any Refresh command and the next Refresh command is 9 x
t
(
driving (
calculation is consistent.
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
t
QHS
RPST
t
nRP
WTR
RPST
t
t
JIT.PER.MAX
JIT.DUTY.MAX
t
t
= RU{
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
is at lease two clocks (2 x
JIT.PER.MAX
JIT.DUTY.MAX
end point and
), or begins driving (
T
CASE
T
t
RPRE
CASE
t
RP
≤ 85 °C.
= 1.1 x
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
/
= 0.6 x
≤ 95 °C.
= + 93 ps, then
t
CK.AVG
= + 93 ps, then
t
t
RPRE
CK.AVG
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
t
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
RPRE
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
t
).
RPRE.MIN(DERATED)
t
t
RPST.MIN(DERATED)
CK
Figure 2
) independent of operation frequency.
shows a method to calculate these points when the device is no longer driving (
=
=
t
RPRE.MIN
t
RPST.MIN
+
+
t
t
JIT.PER.MIN
JIT.DUTY.MIN
t
REFI
19
.
= 0.9 x
Method for Calculating Transitions and Endpoint
= 0.4 x
t
CK.AVG
t
CK.AVG
HYS64T[64/128]02xEDL–[25F/2.5/3S](–)B2
– 72 ps = + 2178 ps and
– 72 ps = + 928 ps and
Small Outlined DDR2 SDRAM Modules
t
nPARAM
= RU{
t
t
JIT.PER
JIT.DUTY
t
t
nRP
RP
t
PARAM
= 15 ns, the device will support
= RU{
of the input clock. (output
t
t
of the input clock. (output
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
/
t
CK.AVG
Internet Data Sheet
t
t
RP
HP
t
/
t
at the input is
JIT.DUTY.MIN
JIT.PER.MIN
t
}, which is in clock
CK.AVG
FIGURE 2
t
RPST
}, which is in
), or begins
=
=
= – 72 ps
= – 72 ps
t
t
RPRE.MAX
RPST.MAX