hys64t128021edl-25fb2 Qimonda, hys64t128021edl-25fb2 Datasheet - Page 4

• Manufacturer Part Number: hys64t128021edl-25fb2
• Description: 200-pin So-dimm Ddr2 Sdram Modules Ddr2 Sdram
• Manufacturer: Qimonda

1) Product released after 2007-08-01 will support
2) For products after 2007-08-01.
1.2
The Qimonda HYS64T[64/128]02xEDL–[25F/2.5/3S](–)B2
module family are Small-Outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules
64M × 64 (512MB) in organization and density, intended for
mounting into 200-pin connector sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–E0" where 6400S
Rev. 1.20, 2008-06
08212006-PKYN-2H1B
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Min. Row Cycle Time
Precharge-All (4 banks) command period
Product Type
PC2-6400 (5-5-5)
HYS64T128021EDL-25FB2
HYS64T64020EDL-25F-B2
PC2-6400 (6-6-6)
HYS64T128021EDL-2.5B2
HYS64T64020EDL-2.5-B2
PC2-5300 (5-5-5)
HYS64T128021EDL-3S-B2
HYS64T64020EDL-3S-B2
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "E".
1)
Description
Compliance Code
1GB 2R×8 PC2–6400S–555–12–E0
512MB 2R×16 PC2–6400S–555–12–A0
1GB 2R×8 PC2–6400S–666–12–E0
512MB 2R×16 PC2–6400S–666–12–A0
1GB 2R×8 PC2–5300S–555–12–E0
512MB 2R×16 PC2–5300S–555–12–A0
in 128M × 64 (1GB),
DDR2
PC2
t
t
RC
PREA
t
RAS
= 40 ns for all DDR2 speed sort.
2)
–25F
–800D
–6400D
5–5–5
52.5
12.5
4
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
–2.5
–800E
–6400E
6–6–6
55
15
HYS64T[64/128]02xEDL–[25F/2.5/3S](–)B2
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
Small Outlined DDR2 SDRAM Modules
–667D
5–5–5
–3S
–5300D
55
15
2
C protocol. The first 128 bytes are
Ordering Information
SDRAM Technology
512Mbit (×8)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
Unit
t
ns
ns
CK
Internet Data Sheet
TABLE 2
Note
2)
Decoupling
2
PROM