hys64t512022edl-25f-a Qimonda, hys64t512022edl-25f-a Datasheet - Page 3

• Manufacturer Part Number: hys64t512022edl-25f-a
• Description: 200-pin Dual-die Small-outline Ddr2 Sdramm Modules
• Manufacturer: Qimonda

1
This chapter gives an overview of the 200-pin Small-Outline DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
• 200-Pin PC2-6400 and PC2-5300 DDR2 SDRAM memory
• 512M × 64 module organization, and 2 ×256M × 8 chip
• 4GB Modules built with 4Gbit (2Gbit Dual-Dies) DDR2
• Standard Double-Data-Rate-Two Synchronous DRAMs
• All speed grades faster than DDR2-400 comply with
• Programmable CAS Latencies (3, 4, 5, 6 and 7 ), Burst
1) This
2) Precharge-All command for an 8 bank device will equal to
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 1.00, 2008-07
07032008-OVFG-HMBJ
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
Precharge-All (8 banks) command period
modules.
organization.
SDRAMs in chipsize packages PG-TFBGA-71.
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
DDR2-400 timing specifications.
Length (8 & 4).
where
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
t
PREA
t
nRP
value is the minimum value at which this chip will be functional.
= RU{
t
RP
Features
/
Overview
t
CK(avg)
} and
CL3
CL4
CL5
CL6
t
RP
is the value for a single bank precharge.
.
DDR2
PC2
f
f
f
f
t
t
t
t
t
CK3
CK4
CK5
CK6
RCD
RP
RAS
RC
PREA
t
RP
–25F
–800D
–6400D
5–5–5
200
266
400
–
12.5
12.5
45
57.5
15
+ 1 ×
3
t
• Auto Refresh (CBR) and Self Refresh.
• Auto Refresh for temperatures above 85 °C
• Programmable self refresh rate via EMRS2 setting.
• Programmable partial array refresh via EMRS2 settings.
• DCC enabling via EMRS2 setting.
• All inputs and outputs SSTL_1.8 compatible.
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
• Serial Presence Detect with E
• SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm
• Based on standard reference layouts Raw Cards 'D'.
• RoHS compliant products
CK
or
Termination (ODT).
wide
t
nRP
–2.5
–800E
–6400E
6–6–6
200
266
333
400
15
15
45
60
17.5
+ 1 × nCK, depending on the speed bin,
Small Outline DDR2 SDRAM Modules
HYS64T512022EDL–[2.5/25F/3S]–A
–667D
5–5–5
–3S
–5300D
200
266
333
–
15
15
45
60
18
1)
.
2
PROM.
Unit
t
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
CK
Performance Table
Internet Data Sheet
TABLE 1
t
REFI
Note
1)2)
= 3.9 μs.