am53c94 Advanced Micro Devices, am53c94 Datasheet - Page 32

• Manufacturer Part Number: am53c94
• Description: High Performance Scsi Controller
• Manufacturer: Advanced Micro Devices

CNTLREG3 – Bit 0 – BS8 – Burst Size 8
The BS8 bit is used to modify the timing of the DREQ
signal with respect to the DMARD and DMAWR signals.
The BS8 bit is used in conjunction with the Modify DMA
Mode (MDM) bit in the CNTLREG3. Both bits have to be
set for proper operation.
When the BS8 bit is set the device delays the assertion
of the DREQ signal until 8 bytes or 4 words transfer is
possible.
When the BS8 bit is set and the device is in a DMA write
mode the DREQ signal will be asserted only when 8 byte
locations are available for writing. In the DMA read
mode the DREQ signal will go active under the following
circumstances:
At the end of a transfer,
In the middle of a transfer
When the BS8 bit is reset and the device is in a DMA
read or write mode the DREQ signal will toggle every
32
In the target mode,
– when the transfer is complete
or
– when the ATN signal is active
In the initiator mode,
– when the Current Transfer Register
or
– after any phase change
In the initiator mode,
– when the last 8 bytes of the FIFO are full
– during Synchronous Data-In transfer when the
AMD
is decremented to zero
Event Transfer Count Register is greater than
7 and the last 8 bytes of the FIFO are full.
P R E L I M I N A R Y
Am53C94/Am53C96
time the data is strobed by the DMARD or DMAWR
signals.
Using Bit 0 (BS8) and Bit 1 (MDM) of Control
Register 3, one can enable the different combination
modes shown in the table below.
Data Alignment Register (0FH) Write
The Data Alignment Register (DALREG) is used if the
first byte of a 16-bit DMA transfer from the SCSI bus to
the host processor is misaligned. Prior to issuing an in-
formation transfer command, the host processor must
set the Data Alignment Enable (DAE) bit in the
CNTLREG2.
DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0
(MDM) (BS8)
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Modified DMA Mode
Normal DMA Mode
Burst Size 8 Mode
Function
Reserved
Synchronous
Maximum
16506C-33
Offset
15
15
7
–