ppc440epx Applied Micro Circuits Corporation (AMCC), ppc440epx Datasheet
ppc440epx
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ppc440epx Summary of contents
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... NAND Flash on the NAND Flash interface. • Optional security feature (PPC440EPx-S). • Available in RoHS compliant, lead-free package. (PPC440EPx-S), and general purpose I/O. Technology: CMOS Cu-11, 0.13μm. Package: 35mm, 680-ball thermally enhanced plastic ball grid array (TE-EPBGA). RoHS compliant package available. ...
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... PPC440EPx Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Floating Point Unit (FPU SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Security Function (optional KASUMI Algorithm (optional PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External Peripheral Bus Controller (EBC Ethernet Controller ...
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... Revision 1.29 – July 22, 2008 Preliminary Data Sheet Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. PPC440EPx Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. 35mm, 680-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 5. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 6. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 7. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 8 ...
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... PPC440EPx Embedded Processor Table 27. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4 Revision 1.29 – July 22, 2008 Preliminary Data Sheet AMCC Proprietary ...
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... The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PPC440EPx User’s Manual for details on accessing these registers. Figure 1. Order Part Number Key ...
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... The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus Address Maps The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs) ...
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... Local Memory USB 2.0 Device USB 2.0 Host On-Chip Memory Security (PPC440EPx-S) 1 PCI 1 EBC 1 PCI AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Sub Function Start Address 0 0000 0000 DDR SDRAM 0 0000 0000 Reserved 0 8000 0000 OPB1 Arbiter 0 E000 0000 Reserved 0 E000 0040 Device Controller ...
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... PPC440EPx Embedded Processor Table 1. System Memory Address Map (Sheet Function Internal Peripherals 1 EBC Boot space Notes: 1. EBC and PCI are relocatable, but this map reflects the suggested configuration. 8 Sub Function Start Address Reserved 1 EF50 0000 General Purpose Timer ...
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... Reserved DMA-to-PLB4 Controller PLB4-to-OPB2 Bridge OPB2-to-PLB4 Bridge Reserved USB 2.0 Host OPB Master DCR Reserved USB 2.0 Host OPB Slave DCR Reserved AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Start Address End Address 000 3FF 000 00B 00C 00D 00E ...
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... PPC440EPx Embedded Processor Table 2. DCR Address Map (Sheet Function On Chip Memory (SRAM Controller) Reserved Notes: 1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 B). ...
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... Single-beat read and write ( bytes for 64-bit masters bytes for 128-bit masters) – 4-word line read and write – 8-word line read and write – Double word read and write bursts for 64-bit masters – Quadword read and write bursts for 128-bit masters AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 11 ...
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... DCR – 32-bit data path – 10-bit address Security Function (optional) The built-in security function (PPC440EPx-S only cryptographic engine attached to the 128-bit PLB with built- in DMA and interrupt controllers. Features include: • Federal Information Processing Standard (FIPS) 140-2 design • ...
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... PCI Host Bus Bridge or an Adapter Device's PCI interface • Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an external arbiter • Support for Message Signaled Interrupts • Simple message passing capability • Asynchronous to the PLB AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 13 ...
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... PPC440EPx Embedded Processor • PCI Power Management 1.1 • PCI register set addressable both from on-chip processor and PCI device sides • Ability to boot from PCI bus memory • Error tracking/status • Supports initiation of transfers of the following types: – Single beat I/O reads and writes – ...
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... Allows external master access to all non-EBC PLB slaves – External master can control EBC slaves for access Ethernet Controller Ethernet support provided by the PPC440EPx interfaces to the physical layer but the PHY is not included on the chip: • Two 10/100/1000 interfaces running in full- and half-duplex modes providing: – ...
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... PPC440EPx Embedded Processor Serial Ports (UART) Features include: • four ports in the following combinations: – One 8-pin (UART0) – Two 4-pin (UART0 and UART1) – One 4-pin (UART0) and two 2-pin (UART1 and UART2) – Four 2-pin (UART0, UART1, UART2, and UART3) • ...
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... General Purpose Timers (GPT) Provides a separate time base counter and additional system timers in addition to those defined in the processor. Features include: • 32-bit Time Base Counter driven by the OPB bus clock • Seven 32-bit compare timers AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 17 ...
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... PPC440EPx Embedded Processor General Purpose IO (GPIO) Controller • Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. • 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. ...
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... AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Part Number Heat Slug PCB Substrate 0.4 - 0.6 1.0 Notes: 9 680 x 0.60 ± 0.10 Solder Ball Logo View ® ...
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... PPC440EPx Embedded Processor Assembly Recommendations Table 3. Recommended Reflow Soldering Profile Profile Feature Average ramp-up rate Preheat • Temperature Min • Temperature Max • Time (min to max) Time Maintained Above: • Temperature • Time Peak Temperature Time within 5°C of Actual Peak Temperature Ramp-down Rate Time 25° ...
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... DM5 DM6 DM7 DM8 [DMAAck0][IRQ8]GPIO47 [DMAAck1][IRQ4]GPIO44 [DMAAck2][PerAddr06]GPIO01 [DMAAck3][PerAddr03]GPIO04 [DMAReq0][IRQ7]GPIO46 [DMAReq1]IRQ5[ModeCtrl] [DMAReq2][PerAddr07]GPIO00 [DMAReq3][PerAddr04]GPIO03 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AP25 Power AP24 AJ03 AK03 DDR SDRAM AP08 AH02 DDR SDRAM AH01 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 2 of 25) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 [DrvrInh1]USB2LS0 [DrvrInh2]Halt EAGND EAV DD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 ...
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... GMC0TxD2] GPIO24 [GMCTxD3, GMC0TxD3] GPIO25 [GMCTxD4, GMC1TxD0] GPIO16 [GMCTxD5, GMC1TxD1] GPIO17 [GMCTxD6, GMC1TxD2] GPIO18 [GMCTxD7, GMC1TxD3] GPIO19 GMCTxEr, GMC1TxCtl GMCTxEn, GMC0TxCtl AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group A04 External Master Peripheral D06 External Master Peripheral AJ32 AK32 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 4 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group E16 E18 E19 E25 E27 E30 E31 H01 H02 H05 H30 H33 K05 K30 N01 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 6 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group W17 W18 W19 W20 W30 W33 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 8 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GPIO19[GMCTxD7, GMC1TxD3] GPIO20[RejectPkt0] GPIO21[RejectPkt1] GPIO22[NFRdyBusy] GPIO23[SCPDO] GPIO24[GMCTxD2, GMC0TxD2] GPIO25[GMCTxD3, GMC0TxD3] [GPIO26]IIC0SData GPIO27[USB2RxErr][ExtReq] GPIO28[USB2TxVal] GPIO29[USB2Susp][HoldAck] GPIO30[USB2XcvrSel][ExtAck] GPIO31[USB2TermSel][BusReq] AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AN34 AP01 AP02 AP03 Power AP32 AP33 AP34 B25 C25 D25 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 10 of 25) Signal Name GPIO32[USB2OM0][PerDataPar2] GPIO33[USB2OM1][PerDataPar3] GPIO34[UART0_DCD/UART1_CTS/UART2_Tx] GPIO35[UART0_DSR/UART1_RTS/UART2_Rx] GPIO36[UART0_CTS/UART3_Rx][PerDataPar0] GPIO37[UART0_RTS/UART3_Tx][PerDataPar1] GPIO38[UART0_DTR/UART1_Tx] GPIO39[UART0_RI/UART1_Rx] GPIO40[IRQ0] GPIO41[IRQ1] GPIO42[IRQ2] GPIO43[IRQ3] GPIO44[IRQ4][DMAAck1] GPIO45[IRQ6][EOT1/TC1] GPIO46[IRQ7][DMAReq0] GPIO47[IRQ8[DMAAck0] GPIO48[IRQ9][EOT0/TC0] GPIO49[TrcBS0] GPIO50[TrcBS1] GPIO51[TrcBS2] ...
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... MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemClkOut MemClkOut AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AC34 IIC1 Peripheral AC32 AD33 AC31 AD34 U34 V32 Interrupts W34 U33 U32 T34 T32 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 12 of 25) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 ...
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... MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemODT0 MemODT1 [ModeCtrl]IRQ5[DMAReq1] AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AF03 AF01 AD04 AD03 AG03 AF02 AE02 AE01 AC03 AC01 AA04 AA03 AD02 AC04 AB01 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 14 of 25) Signal Name [NFALE]GPIO15 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO06 [NFCE2][PerCS2]GPIO07 [NFCE3][PerCS3]GPIO08 [NFCLE]GPIO14 [NFRdyBusy]GPIO22 [NFREn]GPIO12 [NFWEn]GPIO13 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AC06–AC29 AD06–AD29 AE06–AE29 A physical ball does not exist at these ball AF06–AF29 coordinates. AG06–AG29 AH06–AH29 AJ06–AJ29 B05 B12 B23 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 16 of 25) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 ...
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... PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group Y34 Y33 Y32 PCI Y31 AA33 AA34 T31 PCI AB34 PCI K33 PCI J32 PCI ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 18 of 25) Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 ...
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... PerData23[USB2DO7] PerData24[USB2DI0] PerData25[USB2DI1] PerData26[USB2DI2] PerData27[USB2DI3] PerData28[USB2DI4] PerData29[USB2DI5] PerData30[USB2DI6] PerData31[USB2DI7] [PerDataPar0]GPIO36[UART0_CTS/UART3_Rx] [PerDataPar1]GPIO37[UART0_RTS//UART3_Tx] [PerDataPar2]GPIO32[USB2OM0] [PerDataPar3]GPIO33[USB2OM1] [PerErr]GPIO11 PerOE PerReady AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group C14 D14 A13 B13 C13 D13 A12 C12 A11 D12 B11 C11 D11 A10 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 20 of 25) Signal Name PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PSROOut RAS [RcvrInh]USB2RxAct[HoldReq] [RefEn]USB2TxRdy [RejectPkt0]GPIO20 [RejectPkt1]GPIO21 SCPClkOut[IIC1SClk] SCPDI[IIC1SData] [SCPDO]GPIO23 SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV ...
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... TRST [UART0_CTS/UART3_Rx]GPIO36[PerDataPar0] [UART0_DCD/UART1_CTS/UART2_Tx]GPIO34 [UART0_DSR/UART1_RTS/UART2_Rx]GPIO35 [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 [UART0_RTS/UART3_Tx]GPIO37[PerDataPar1] UART0_Rx UARTSerClk UART0_Tx AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group B22 JTAG C09 System C16 System D16 P03 System K02 JTAG AE34 AE32 Trace AE33 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 22 of 25) Signal Name U1AV DD U1AV DD U2AV DD U2AV DD U1AGND U1AGND U2AGND U2AGND UA2GND USB2Clk [USB2DI0]PerData24 [USB2DI1]PerData25 [USB2DI2]PerData26 [USB2DI3]PerData27 [USB2DI4]PerData28 [USB2DI5]PerData29 [USB2DI6]PerData30 [USB2DI7]PerData31 [USB2DO0]PerData16 [USB2DO1]PerData17 [USB2DO2]PerData18 [USB2DO3]PerData19 [USB2DO4]PerData20 [USB2DO5]PerData21 [USB2DO6]PerData22 [USB2DO7]PerData23 USB2LS0[DrvrInh1] USB2LS1[LeakTest][HoldPri] ...
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... Revision 1.29 – July 22, 2008 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 23 of 25) Signal Name [USB2XcvrSel]GPIO30[ExtAck] USB2Xcvr USB2Xcvr USB2XtalIn USB2XtalOut AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group M03 Universal Serial Bus J02 Universal Serial Bus J01 N02 Universal Serial Bus ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 24 of 25) Signal Name ...
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... In the following table, only the primary (default) signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what other signals or functions are on those balls, look up the primary signal name in Table 5 on page 21. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AA05 ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball A01 GND B01 A02 GND B02 A03 GND B03 A04 GPIO27* B04 A05 USB2Clk B05 A06 TRST B06 A07 PerClk B07 A08 GPIO10* B08 A09 ...
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... F29 DD E30 GND F30 E31 GND F31 E32 Halt* F32 OV E33 F33 DD E34 PCIAD06 F34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name PerData25* G01 PerData29* PerData24* G02 PerData28* PerData23* G03 PerData26* PerData22* G04 PerData27 G05 ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball J01 USB2Xcvr K01 J02 USB2Xcvr K02 J03 U2AGND K03 U2AV J04 K04 DD OV J05 K05 DD J06 No Ball K06 J07 No Ball K07 J08 No Ball K08 J09 ...
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... P29 V N30 P30 DD N31 PCIAD21 P31 N32 PCIAD23 P32 N33 PCIAD22 P33 N34 PCIC3/BE3 P34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name USB2LS1* R01 MemData59 TCK R02 USB2LS0* TmrClk R03 GPIO32* GPIO31* R04 GPIO33 R05 ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball U01 MemData56 V01 U02 MemData57 V02 U03 DM7 V03 U04 DQS7 V04 U05 GND V05 U06 No Ball V06 U07 No Ball V07 U08 No Ball V08 U09 ...
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... No Ball AB29 V AA30 AB30 DD AA31 PCIReset AB31 AA32 PCIClk AB32 AA33 PCIGnt4 AB33 AA34 PCIGnt5 AB34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name MemData46 AC01 MemData41 SOV MemData47 AC02 DD DM5 AC03 MemData40 DQS5 AC04 MemData45 V V AC05 ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AE01 MemData39 AF01 AE02 MemData38 AF02 AE03 DQS4 AF03 AE04 DM4 AF04 AE05 GND AF05 AE06 No Ball AF06 AE07 No Ball AF07 AE08 No Ball AF08 AE09 ...
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... AK29 EOV AJ30 AK30 DD AJ31 GMCRxDV* AK31 AJ32 GMCCD* AK32 AJ33 GMCRefClk* AK33 AJ34 GPIO62* AK34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name MemClkOut AL01 MemClkOut SOV AL02 MemAddr10 DD BA1 AL03 GND GND AL04 GND GND ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AN01 GND AP01 AN02 GND AP02 AN03 GND AP03 AN04 GND AP04 SOV AN05 AP05 DD AN06 MemAddr05 AP06 AN07 MemAddr07 AP07 AN08 GND AP08 AN09 ...
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... In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address pins (PerAddr) are used as outputs by the PPC440EPx to broadcast an address to external slave devices when the PPC440EPx has control of the external bus. When, during normal operation, an external master gains ownership AMCC Proprietary 440EPx – ...
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... PPC440EPx Embedded Processor of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440EPx. In this example, the pins are also bidirectional, serving both as inputs and outputs. Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown ...
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... Indicates the current target is requesting the master to stop the current transaction. PCIStop (PCI 2.2 specification requires 8.2K I ndicates the target agent’s ability to complete the current data phase of the transaction. PCITRDY (PCI 2.2 specification requires 8.2K AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description . Ω ...
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... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... GMCGTxClk, GMII: Transmit clock for GMII. GMC0TxClk RGMII 0: Transmit clock. GMCRefClk, GMII, RGMII: Reference clock. SMIIRefClk SMII: Reference clock. RejectPkt0:1 External request to reject a packet. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description I/O Type Notes 3 ...
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... PerData00:31 Note: PerData00 is the most significant bit (msb) on this bus. Peripheral data bus parity used by the PPC440EPx when not in PerDataPar0:3 external master mode; otherwise, used by external master. Used by either the peripheral controller, DMA controller, or PerBLast external master to indicates the last transfer of a memory access ...
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... If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440EPx needs to regain BusReq control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440EPx to indicate ExtAck that a data transfer occurred ...
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... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... Test Mode Select. Test Reset. Note: Must be asserted low during a power-on system reset in TRST order to reset the JTAG interface. If the JTAG interface is not reset, the processor may not boot. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet) ...
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... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... USB PHY (analog). U2AV DD Connect to OV Ground for USB PLL (analog) voltage. U1AGND Connect to GND. Ground for USB PHY (analog) voltage. U2AGND Connect to GND. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description . ...
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... PPC440EPx Embedded Processor Device Characteristics Table 9. Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings ...
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... The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440EPx. See “Absolute Maximum Ratings” on page 66. 4. Startup sequencing of the power supply voltages is not required. A power-down cycle must complete (OV DD and V DD are below +0 ...
Page 68
... PPC440EPx Embedded Processor Table 11. Input Capacitance Parameter 2.5V/1.8V DDR 3.3V LVTTL PCI 3.3V tolerant CMOS USB Figure 4. Overshoot Waveform AC Overshoot (V) DC Overshoot (V) DC Undershoot (V) AC Undershoot ( Table 12. Overshoot and Undershoot Receiver AC Overshoot (V) 3.3V LVTTL 3.9 2.5V (3.3V tolerant) 3.9 1.2*SOV DDR DD 1.2*OV PCI DD Notes the period of the bus clock. ...
Page 69
... The analog voltages (AVdd, EAVdd, and UnAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before the PPC440EPx. A Separate filter, as shown below, is recommended for each voltage. • The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +50 mV. • ...
Page 70
... PPC440EPx Embedded Processor Table 15. V Supply Power Dissipation DD Frequency (MHz) 400 533 667 Notes: 1. Power is measured and is based each function with representative traffic. Table 16. DC Power Supply Loads Parameter V (+1.5V) active operating current DD OV (+3.3V) active operating current DD EOV (+2.5V) active operating current ...
Page 71
... The following heat sink was used in the above thermal analysis: ALPHA LPD35-15B (35mm x 35mm x15mm) The heat sink is manufactured by: Alpha Novatech, Inc. (www.alphanovatech.com) 473 Sapena Court, #12 Santa Clara, CA 95054 Phone: 408-567-8082 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Airflow ft/min (m/sec) Symbol 0 100 200 (0) (0 ...
Page 72
... Note: V and V should be specified in Volts. I BE2 BE1 same. The small values require precision measurement and current sources. The calculated on chip (ball to ball) series resistance for the PPC440EPx thermal monitor circuit is 2.0 ohms. The thermal sensor reflects the PPC440EPx junction temperature. PPC440EPx C TherMonA E ...
Page 73
... T High time CH MAL Clock F Frequency C T Period C Figure 5. Timing Waveform SysClk and GMCRefClk are 2.5V (3.3V tolerant). Slew rate should be measured between 0.7V and 1.7V. Note: AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Min Max 333.33 666.66 1.5 3 133.33 166.66 6 7.5 45% of nominal 55% of nominal period period 45 83 ...
Page 74
... The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected the system designer to ensure that any SSCG used with the PPC440EPx meets the above Important: requirements and does not adversely affect other aspects of the system. 74 Revision 1.29 – ...
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... GMCRxClk high time GMCRxClk low time GMCRefClk frequency GMCRefClk period GMCRefClk high time GMCRefClk low time GMCRefClk Edge Stability (cycle-to-cycle jitter) GMCRefClk Slew Rate AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Min Max – 66.66 15 – 40% of nominal period 60% of nominal period ...
Page 76
... PPC440EPx Embedded Processor Table 19. Peripheral Interface Clock Timings (Sheet Parameter PerClk (and OPB Clock) frequency (for ext. master or sync. slaves) PerClk period PerClk high time PerClk low time UARTSerClk frequency UARTSerClk period UARTSerClk high time UARTSerClk low time ...
Page 77
... Drive level: 50–500μW − 2(C ) where L Stray C is the load capacitance required by the crystal for oscillation the board parasitic capacitance Stray AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Min – 10 40% of nominal period 40% of nominal period USB2XtalOUT USB2XtalIn C Max Units Notes 100 MHz – ...
Page 78
... PPC440EPx Embedded Processor Figure 6. Input Setup and Hold Waveform Clock 1.25V(1.5V) Inputs Figure 7. Output Delay and Float Timing Waveform Clock 1.25V(1.5V) T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive min T min IS IH Valid T max OV T min ...
Page 79
... Outputs OV High (Drive) Float (High-Z) Valid Low (Drive) RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnTxClk. RGMII 10/100Mb timing is with reference only to the raising edge of GMCnTxClk. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor T T min min min ...
Page 80
... PPC440EPx Embedded Processor Table 20. I/O Specifications—PCI, USB, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. SMIISync is a weak driver. Redrive SMIISync when driving more than one load. ...
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... SCPDO UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RI UARTn_RTS USB2Xcvr USB2Xcvr USB2DI0:7 4 USB2DO0:7 USB2LS0:1 4 USB2OM0:1 USB2RxAct 4 USB2RxDV USB2RxErr USB2Susp USB2TermSel USB2TxRdy 4 USB2TxVal AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min 0.5 3.5 0.5 3 0.5 3.5 0.5 3 ...
Page 82
... PPC440EPx Embedded Processor Table 20. I/O Specifications—PCI, USB, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. SMIISync is a weak driver. Redrive SMIISync when driving more than one load. ...
Page 83
... External Master Peripheral Interface BusReq ExtAck ExtReq 4 ExtReset HoldAck HoldReq 4 HoldPri 4 PerClk PerErr 4 NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy 4 NFREn NFWEn AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min ...
Page 84
... The paths (traces) for the data and the associated data strobe signal should be routed with the same length between the PPC440EPx and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the capture logic at the same time the data is in transition. All of the following timing assumes a trace velocity of 167ps/in ...
Page 85
... PPC440EPx) between the DQS/DQ/DM and the clock (assuming nominal settings as specified in the PPC440EPx Users Manual). While the clock is now 500ps later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for T (± ...
Page 86
... PPC440EPx Embedded Processor Table 22. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:63 ECC0:7 DM0:8 MemClkOut MemAddr00:13 BA0:2 RAS CAS WE BankSel0:1 ClkEn DQS0:8 MemODT0:1 DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is generated by means of simulation and includes logic, driver, package RLC, and lengths ...
Page 87
... All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle. 2. Clock speed is 166MHz. Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor ...
Page 88
... PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices. In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version of DQS. The amount of delay is user programmable. In the example shown in Figure 12, the delay is set to approximately 25% of the system clock ...
Page 89
... Revision 1.29 – July 22, 2008 Preliminary Data Sheet constant. Figure 12. DDR SDRAM DQS Read Timing MemClkOut DQS MemData Delayed DQS (data strobe) AMCC Proprietary 440EPx – PPC440EPx Embedded Processor DQS delay 89 ...
Page 90
... PPC440EPx Embedded Processor Initialization The PPC440EPx provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). ...
Page 91
... AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Contents of Modification Initial creation of document. Add “Preliminary—Subject to Change” watermark. Change maximum NAND Flash to 256MB. Update with signal-to-pin assignment and I/O circuit type specifications. Replace existing DDR SDRAM information with new DDR2 SDRAM information. ...
Page 92
... PPC440EPx Embedded Processor Date Version 12/28/2006 1.18 01/10/2007 1.19 02/01/2007 1.20 03/12/2007 1.21 04/23/2007 1.22 07/18/2007 1.23 08/06/2007 1.24 08/24/2007 1.25 10/15/2007 1.26 01/072008 1.27 03/18/2008 1.28 07/22/2008 1.29 92 Contents of Modification Indicate that two USB analog voltages are needed with separate filters. Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals. ...
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... Revision 1.29 – July 22, 2008 Preliminary Data Sheet AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 93 ...
Page 94
... PPC440EPx Embedded Processor 94 Revision 1.29 – July 22, 2008 Preliminary Data Sheet AMCC Proprietary ...
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... SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation. All Rights Reserved. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Applied Micro Circuits Corporation http://www.amcc.com 95 ...
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... PPC440EPx Embedded Processor 96 Revision 1.29 – July 22, 2008 Preliminary Data Sheet AMCC Proprietary ...