km432s2030c Samsung Semiconductor, Inc., km432s2030c Datasheet
km432s2030c
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km432s2030c Summary of contents
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... KM432S2030C SDRAM 512K x 32bit x 4 Banks Samsung Electronics reserves the right to change products or specification without notice. Synchronous DRAM LVTTL Revision 1.1 March 1999 - 1 - CMOS SDRAM REV. 1.1 Mar. '99 ...
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... Revision 0.3 (March 5th, 1999) - Preliminary Spec Revision 0.2 (February 13th, 1999) • Removed KM432S2030C-7@CL2 part (115MHz@CL2) • Changed VDD condition of KM432S2030C-8@CL2 from 3.135V to 3.0V~3.6V. • Changed AC Characteristic table format • Add KM432S2030C-Z part. Revision 0.1 (December 2nd, 1998) • ...
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... LCBR CLK CKE GENERAL DESCRIPTION The KM432S2030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized 524,288 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle ...
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... KM432S2030C PIN CONFIGURATION (Top view DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 N DQM0 WE CAS RAS CS N.C BA0 BA1 A10/ DQM2 V DD N.C DQ16 V SSQ DQ17 DQ18 V DDQ DQ19 DQ20 V SSQ DQ21 DQ22 V DDQ DQ23 V DD ...
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... KM432S2030C PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable Address 0 10 BA0,1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 3 Data input/output mask DQ ~ Data input/output Power supply/ground ...
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... Any input DDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled OUT 5. The VDD condition of KM432S2030C-6 is 3.135V~3.6V. DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active) I ...
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... Output load condition 3.3V 1200 Output 50pF 870 (Fig output load circuit Note : 1. The DC/AC Test Output Load of KM432S2030C-6/7 is 30pF. 2. The VDD condition of KM432S2030C-6 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter CLK cycle time Row active to row active delay RAS to CAS delay ...
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... KM432S2030C Symbol CL t CC(min) t RRD(min) t RCD(min) t RP(min) t RAS(min) t RAS(max min 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change case of row precharge interrupt, auto precharge and read burst stop. 5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code " ...
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... KM432S2030C SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable ...
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... KM432S2030C MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address / RFU RFU W.B.L Function Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 1 Reserved Write Burst Length Length Burst 1 Single Bit POWER UP SEQUENCE 1. Apply power and start clock, Attempt to maintain CKE= " ...
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... KM432S2030C BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address ...
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... KM432S2030C DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...
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... KM432S2030C DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The ...
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... KM432S2030C DEVICE OPERATIONS (Continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle ...
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... KM432S2030C BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4 CLK CMD WR CKE Internal CKE DQ(CL2 DQ(CL3 Not Written 2. DQM Operation 1) Write Mask (BL=4) CLK WR CMD DQM DQ(CL2 DQ(CL3 DQM to Data-in Mask = 0 ...
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... KM432S2030C 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note ADD tCDL Note 3 *Note : 1. By " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... KM432S2030C 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iv) CMD DQM DQ (b) CL=3, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iii) CMD DQM DQ RD iv) CMD DQM DQ *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. ...
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... KM432S2030C 5. Write Interrupted by Precharge & DQM CLK WR CMD DQM *Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code " ...
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... KM432S2030C 8. Burst Stop & Interrupted by Precharge 1) Normal Write (BL=4) CLK WR CMD DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS 1) Mode Register Set CLK Note 4 CMD PRE tRP *Note : CLK RDL CLK ; Last data in to burst stop delay. ...
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... KM432S2030C 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK CMD 11. Auto Refresh & Self Refresh 1) Auto Refresh & Self Refresh Note 3 CLK Note 4 CMD PRE CKE tRP 2) Self Refresh Note 6 CLK ...
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... KM432S2030C 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic MODE 4 8 Full Page Special BRSW MODE Random Burst Stop MODE RAS Interrupt (Interrupted by Precharge) Interrupt ...
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... KM432S2030C FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State IDLE Row Active Read ...
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... KM432S2030C FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State Row Activating Refreshing Mode Register Accessing Abbreviations : RA = Row Address NOP = No Operation Command *Note : 1 ...
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... KM432S2030C FUNCTION TRUTH TABLE (TABLE 2) CKE Current CKE CS (n-1) n State Self Refresh All Banks Precharge Power Down All ...
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... KM432S2030C Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH CLOCK tCC CKE *Note 1 CS tRCD tSH RAS tSS tSH CAS tSS tSH ADDR Ra Ca tSS *Note 2 *Note 2 /AP Ra *Note 3 10 tRAC DQ WE DQM Row Active ...
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... KM432S2030C *Note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1 BA0 BA1 Enable and disable auto precharge function are controlled by A10/AP in read/write command ...
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... KM432S2030C Power Up Sequence CLOCK CKE High level is necessary CS tRP RAS CAS ADDR /AP 10 High DQM High level is necessary Precharge Auto Refresh (All Banks ¡ó tRC ¡ó ¡ó ¡ó ¡ó ...
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... KM432S2030C Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD RAS CAS Ra Ca ADDR /AP 10 CL=2 tRAC *Note 3 DQ CL=3 tRAC *Note 3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. ...
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... KM432S2030C Page Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD RAS CAS ADDR /AP 10 CL=2 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention ...
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... KM432S2030C Page Read Cycle at Different Bank @Burst Length CLOCK CKE *Note 1 CS RAS CAS ADDR RAa RBb CAa /AP RAa RBb 10 CL=2 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) Row Active (B-Bank) *Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. ...
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... KM432S2030C Page Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS RAa RBb CAa ADDR /AP RAa RBb 10 DAa0 DAa1 DAa2 DQ WE DQM Row Active Write (A-Bank) (A-Bank) Row Active (B-Bank) *Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. ...
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... KM432S2030C Read & Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS ADDR RAa CAa /AP RAa 10 CL=2 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. t should be met to complete write. CDL HIGH RDb ...
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... KM432S2030C Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE CS RAS CAS RAa ADDR RBb /AP RAa RBb 10 DQ (CL=2) DQ (CL=3) WE DQM Row Active Auto Precharge (A-Bank) Row Active (B-Bank) *Note : t 1. should be controlled to meet minimum RCD (In the case of Burst Length=1 & ...
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... KM432S2030C Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE CS RAS CAS ADDR / CL=2 CL=3 WE DQM Read with Row Active Auto Pre (A-Bank) (A-Bank) Row Active (B-Bank) *Note: * When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. ...
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... KM432S2030C Read & Write Cycle with Auto Precharge III @Burst Length CLOCK CKE CS RAS CAS ADDR / CL=2 CL=3 WE DQM Row Active (A-Bank) Auto Precharge *Note : * Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point ...
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... KM432S2030C Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length CLOCK CKE CS RAS CAS ADDR / DQM Row Active Read *Note : 1. DQM is needed to prevent bus contention Qa0 Qa1 Qa2 ...
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... KM432S2030C Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page CLOCK CKE CS RAS CAS RAa CAa ADDR /AP RAa 10 CL=2 DQ CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. ...
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... KM432S2030C Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page CLOCK CKE CS RAS CAS ADDR RAa CAa RAa A / DAa0 DAa1 DAa2 DAa3 DAa4 WE DQM Row Active Write (A-Bank) (A-Bank) *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. ...
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... KM432S2030C Burst Read Single bit Write Cycle @Burst Length CLOCK *Note 1 CKE CS RAS CAS ADDR RAa CAa /AP RAa 10 CL=2 DAa0 DQ CL=3 DAa0 WE DQM Row Active Row Active (A-Bank) Write (A-Bank) *Note : 1. BRSW modes is enabled by setting A At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. ...
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... KM432S2030C Active/Precharge Power Down Mode @CAS Latency=2, Burst Length ¡ó CLOCK ¡ó tSS *Note 1 *Note 2 CKE *Note 3 ¡ó CS ¡ó ¡ó RAS ¡ó ¡ó CAS ¡ó ¡ó ADDR ¡ó ¡ó ...
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... KM432S2030C Self Refresh Entry & Exit Cycle CLOCK *Note 2 *Note 1 CKE tSS CS RAS CAS ADDR Hi-Z WE DQM Self Refresh Entry *Note : TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. ...
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... KM432S2030C Mode Register Set Cycle CLOCK HIGH CKE CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra DQ Hi-Z WE DQM MRS New Command * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & ...
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... KM432S2030C PACKAGE DIMENSIONS 86-TSOP2-400F #86 #1 0.10 MAX 0.004 0. 0.20 0.024 #44 #43 22.62 MAX 0.891 22.22 0.10 0.21 0.05 0.875 0.004 0.008 0.002 0.50 +0.10 0.0197 -0. CMOS SDRAM Unit : Millimeters 0~8 C 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 1.00 1.20 0.10 MAX 0.039 0.047 0.004 0.05 MIN 0.010 REV. 1.1 Mar. '99 ...