km432s2030c Samsung Semiconductor, Inc., km432s2030c Datasheet - Page 29

• Manufacturer Part Number: km432s2030c
• Description: 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

DQ
CLOCK
KM432S2030C
Page Read & Write Cycle at Same Bank @Burst Length=4
A
ADDR
DQM
10
CKE
RAS
CAS
BA
BA
/AP
WE
CS
CL=2
CL=3
0
1
*Note :
0
Row Active
(A-Bank)
Ra
Ra
1
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
before end of burst. Input data after Row precharge cycle will be masked internally.
command to avoid bus contention.
tRCD
2
3
(A-Bank)
Read
Ca
4
5
(A-Bank)
Read
Qa0
Cb
6
Qa1
Qa0
7
Qb0
Qa1
8
Qb0
Qb1 Qb2
*Note 1
9
RDL
HIGH
Qb1
10
before Row precharge, will be written.
11
(A-Bank)
Write
Dc0
Dc0
Cc
12
tCDL
Dc1
Dc1
13
(A-Bank)
Write
Dd0
Dd0
Cd
14
Dd1
Dd1
15
tRDL
*Note 2
*Note 3
REV. 1.1 Mar. '99
CMOS SDRAM
16
*Note 4
Precharge
(A-Bank)
17
18
: Don't care
19