m366s6453cts Samsung Semiconductor, Inc., m366s6453cts Datasheet

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m366s6453cts

Manufacturer Part Number
m366s6453cts
Description
Pc133/pc100 Unbuffered Dimm
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
M366S6453CTS
M366S6453CTS SDRAM DIMM
64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
Dynamic RAM high density memory module. The Samsung
M366S6453CTS consists of sixteen CMOS 32M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
The M366S6453CTS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
PIN CONFIGURATIONS (Front side/back side)
Synchronous design allows precise cycle control with the use of
Pin
The Samsung M366S6453CTS is a 64M bit x 64 Synchronous
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
DQM0
Front
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
*CB0
*CB1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
V
V
V
V
V
V
WE
NC
NC
DD
DD
DD
SS
SS
SS
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
A10/AP
DQM1
DQM2
DQM3
Front
CLK0
DQ16
DQ17
*CB2
*CB3
CS0
CS2
BA1
V
V
V
V
V
V
DU
DU
DU
NC
NC
A0
A2
A4
A6
A8
SS
DD
DD
SS
DD
SS
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
**SDA
DQ18
DQ19
DQ20
*V
CKE1
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
**SCL
Front
CLK2
*WP
V
V
V
V
V
V
NC
NC
DD
REF
DD
DD
SS
SS
SS
100
101
102
103
104
105
106
107
108
109
110
111
112
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DQM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Back
*CB4
*CB5
CAS
V
V
V
V
V
V
NC
NC
DD
DD
DD
SS
SS
SS
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Pin
DQM5
DQM6
DQM7
CKE0
DQ48
DQ49
CLK1
Back
*CB6
*CB7
*A13
RAS
CS1
BA0
CS3
A11
V
A12
V
V
V
V
NC
NC
A1
A3
A5
A7
A9
SS
DD
SS
DD
SS
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
FEATURE
• Performance range
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
M366S6453CTS-L7C/C7C
M366S6453CTS-L1H/C1H
M366S6453CTS-L7A/C7A
M366S6453CTS-L1L/C1L
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
system clock
DQ50
DQ51
DQ52
*V
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
**SA0
**SA1
**SA2
PC133/PC100 Unbuffered DIMM
CLK3
Back
V
V
V
V
V
V
NC
NC
NC
DD
REF
DD
DD
SS
SS
SS
Part No.
0.3V power supply
PIN NAMES
*
** These pins should be NC in the system
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0 ~ CLK3
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS3
RAS
CAS
WE
DQM0 ~ 7
V
V
*V
SDA
SCL
SA0 ~ 2
*WP
DU
NC
DD
SS
These pins are not used in this module.
Pin Name
REF
which does not support SPD.
133MHz@CL=3/100MHz@CL=2
REV. 0.0 Sept. 2001
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Address in EEPROM
Write protection
Don t use
No connection
Max Freq. (Speed)
100MHz @ CL=2/3
133MHz@CL=2/3
100MHz @ CL=3
Function

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m366s6453cts Summary of contents

Page 1

... GENERAL DESCRIPTION The Samsung M366S6453CTS is a 64M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S6453CTS consists of sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate ...

Page 2

... M366S6453CTS PIN CONFIGURATION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable A0 ~ A12 Address BA0 ~ BA1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 Data input/output mask DQ0 ~ 63 Data input/output V /V Power supply/ground ...

Page 3

... M366S6453CTS FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 DQM CS DQ0 DQ0 DQ1 DQ1 DQ2 DQ2 U0 DQ3 DQ3 DQ4 DQ4 DQ5 DQ5 DQ6 DQ6 DQ7 DQ7 DQM1 DQM CS DQ8 DQ0 DQ9 DQ1 DQ10 DQ2 U1 DQ11 DQ3 DQ12 DQ4 DQ13 DQ5 DQ14 DQ6 DQ15 ...

Page 4

... M366S6453CTS ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. ...

Page 5

... M366S6453CTS DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active Precharge standby cur- CC2 rent in power-down mode I PS CC2 I N CC2 Precharge standby cur- rent in non power-down mode I NS CC2 I P Active standby current in ...

Page 6

... M366S6453CTS AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200 Output 50pF 870 (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...

Page 7

... M366S6453CTS AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter Symbol CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width ...

Page 8

... M366S6453CTS SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Auto precharge disable Read & column address Auto precharge enable Auto precharge disable Write & column address Auto precharge enable ...

Page 9

... M366S6453CTS PACKAGE DIMENSIONS 0.118 (3.000) A .118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890) .450 (11.430) 0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) Detail A Tolerances : .005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOP SDRAM Part No. :K4S560832C PC133/PC100 Unbuffered DIMM 5 ...

Page 10

... M366S6453CTS M366S6453CTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L • Organization : 64MX64 • Composition : 32MX8 *16 • Used component part # : K4S560832C-TL7C/7A/1H/1L,TC7C/7A/1H/1L • rows in module : 2row • banks in component : 4 banks • Feature : 1,375 mil height & double sided component • Refresh : 8K/64ms • Contents : Byte#. Function described bytes written into serial memory at module manufacturer ...

Page 11

... M366S6453CTS SERIAL PRESENCE DETECT INFORMATION Byte # Function described 35 Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM configuration) ...

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