hdmp-1526 ETC-unknow, hdmp-1526 Datasheet - Page 11

• Manufacturer Part Number: hdmp-1526
• Description: Fibre Channel Transceiver Chip
• Manufacturer: ETC-unknow

TRx I/O Definition
692
GND_TXTTL
ENBYTSYNC
VCC_TXTTL
GND_TXA
VCC_TXA
-LCKREF
LOOPEN
TXCAP1
TXCAP0
VCC_TX
REFCLK
VCC_RX
Name
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
GND
Pin
14
11
12
13
10
15
16
17
18
19
20
59
21
25
58
22
23
28
57
24
27
1
2
3
4
6
7
8
9
5
Type
I-TTL
I-TTL
I-TTL
I-TTL
I-TTL
C
S
S
S
S
S
S
S
TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells
of the transmitter section.
Data Inputs: One, 10 bit, pre-encoded data byte. TX[0] is the first bit
transmitted. TX[0] is the least significant bit.
TTL Power Supply: Normally 5 volts. Used for all TTL transmitter input
buffer cells.
Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Loop Filter Capacitor: A loop filter capacitor must be connected across
the TXCAP1 and TXCAP0 pins (typical value = 0.01 F).
Analog Power Supply: Normally 5 volts. Used to provide a clean supply
line for the PLL and high-speed analog cells.
Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
Logic Power Supply: Normally 5 volts. Used for internal transmitter
PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
Logic Ground: Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
Reference Clock and Transmit Byte Clock: A 106.25 MHz clock supplied
by the host system. The transmitter section accepts this signal as the
frequency reference clock. It is multiplied by 10 to generate the serial bit
clock and other internal clocks. The transmit side also uses this clock as
the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It
also serves as the reference clock for the receive portion of the
transceiver. When -LCKREF is activated, the receiver PLL frequency
locks to this reference signal.
Logic Power Supply: Normally 5 volts. Used for internal receiver PECL
logic. It should be isolated from the noisy TTL supply as well as possible.
Enable Byte Sync Input: When high, enables the internal byte sync
function to allow clock synchronization to a comma character (or a
K28.5 character) of positive disparity (0011111010). When the line is
low, the function is disabled and will not reset registers and clocks, or
strobe the BYTSYNC line.
Lock to Reference: When low, causes the PLL to acquire frequency lock
on the external reference, supplied at REFCLK.
DOUT outputs are held static. When set low,
DIN inputs are active.
Signal
DOUT outputs and