hdmp-1526 ETC-unknow, hdmp-1526 Datasheet - Page 5

• Manufacturer Part Number: hdmp-1526
• Description: Fibre Channel Transceiver Chip
• Manufacturer: ETC-unknow

HDMP-1526 (Receiver Section)
Timing Characteristics
T
Notes:
1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
2. Tested using C
3. The RBC clock skew is calculated as t
4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
Figure 5. Receiver Section.
Figure 6. Receiver Latency.
686
C
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
f_lock_rate
= 0 C to +85 C, V


 
b_sync
t
RX[0]-RX[9]
valid_before
t
t_rxlat
f_lock
Symbol
BYTSYNC
valid_after
t
RX[0]-RX[9]
A-B
t
duty
RBC1
RBC0
t-VALID BEFORE
RBC1/0
[3]
[1,2]
[2]
± DIN
[4]






 

[2]
PLL
= 0.01 F.
R5
R6
CC
Bit Sync Time
Frequency Lock Time
(from Time of Setting -LCKREF = 0)
Frequency Lock Rate (when -LCKREF = 0)
Time Data Valid Before Rising Edge of RBC
Time Data Valid After Rising Edge of RBC
RBC Duty Cycle
Rising Edge Time Difference
Receiver Latency
DATA BYTE C
K28.5
= 4.5 V to 5.25 V
R7
R8

 
A-B(max)
t-VALID AFTER
R9
R0
Parameter
- t
DATA
A-B(min)
R1
R2
DATA BYTE A
.
R3
DATA BYTE D


 




R4
DATA
R5
t_RXLAT

 
R6
R7
R8
kHz/ sec
DATA
Units
R9
nsec
nsec
nsec
nsec
bits
bits
sec
%

 
Min.
1.5
8.9
DATA BYTE D
R2
40
3
DATA
R3
R4
Typ.
25.0
26.6
200
5.8
3.3
9.4
R5
1.4 V
Max.
2500
1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
1.4 V
33.9
500
9.9
60
36