hyb514400bj-50 Infineon Technologies Corporation, hyb514400bj-50 Datasheet
hyb514400bj-50
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hyb514400bj-50 Summary of contents
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Dynamic RAM Advanced Information • 1 048 576 words by 4-bit organization • operating temperature • Fast Page Mode Operation • Performance: t RAS access time RAC t CAS access time CAC t Access ...
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... Schottky TTL. Ordering Information Type Ordering Code HYB 514400BJ-50 Q67100-Q973 HYB 514400BJ-60 Q67100-Q756 Semiconductor Group Package Descriptions P-SOJ-26/20-2 300 mil DRAM (access time 50 ns) P-SOJ-26/20-2 300 mil DRAM (access time 60 ns) 2 HYB 514400BJ-50/- DRAM 1998-10-01 ...
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... Read/Write Input OE Output Enable I/O1 - I/O4 Data Input/Output V Power Supply (+ Ground ( N.C. No Connection Semiconductor Group P-SOJ-26/20 I/O3 RAS 4 23 CAS SPP02797 3 HYB 514400BJ-50/- DRAM 1998-10-01 ...
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... Buffers (10) No.1 Clock RAS Generator Block Diagram Semiconductor Group HYB 514400BJ-50/-60 I/O1 I/O2 I/O3 I/O4 Data In Data Out Buffer Buffer 4 10 Sense Amplifier . . . 10 Row Memory Array 1024 Decoder 1024 . . . Substrate Bias Generator DRAM OE 4 Column Decoder 4 I/O Gating 1024 1024 SPB02798 1998-10-01 ...
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... V 2 – 1.0 0 2.4 – – 0 – – – 120 – 110 – – 120 – 110 – 80 – – – 120 – 110 1998-10-01 4 DRAM ...
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... CSH t 5 CRP – REF t – RAC t – CAC t – – OEA 6 HYB 514400BJ-50/- DRAM Limit Values Unit min. max. – – – Limit Values Unit Note -60 – 110 – ns – 40 – ns 10k ...
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... CWL 131 RWC t 68 RWD t 31 CWD t 43 AWD t 13 OEH HYB 514400BJ-50/- DRAM Limit Values Unit -50 -60 – 30 – ns – 0 – ns – 0 – ns – 0 – ns – 0 – – ...
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... PRWC t 48 CPWD t 10 CSR t 10 CHR t 5 RPC t 10 WRP t 10 WRH t 35 CPT t 10 WTS t 10 WTH 8 HYB 514400BJ-50/- DRAM Limit Values Unit -50 -60 30 – 200k 60 200k ns – 35 – ns – 80 – ns – 55 – ns – 10 – ns – 10 – ns – ...
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... They are included in the CPWD t t WCS WCS (MIN and AWD (MIN.) CPWD CPWD (MIN.) 9 HYB 514400BJ-50/- DRAM I it can be changed once CC4 can be met specified as RCD (MAX.) t limit, then access time is RCD (MAX.) t can be met. is specified as RAD (MAX.) t limit, then access time is RAD (MAX ...
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... RCD RSH t CAS t t RAD RAL t t CAH ASC Column t RAH t RCS OEA t DZC t DZO t CAC t CLZ Hi Z Valid Data OUT t RAC 10 HYB 514400BJ-50/- DRAM CRP t ASR Row t RCH t RRH t CDD t ODD t OFF t OEZ Hi Z SPT03025 1998-10-01 ...
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... Write Cycle (Early Write) Semiconductor Group RAS t CSH t t RCD RSH t CAS t t RAD RAL t t CAH ASC Column t CWL t WCS WCH t RWL Valid Data HYB 514400BJ-50/- DRAM CRP t ASR Row SPT03026 1998-10-01 ...
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... RAS t CSH t t RCD RSH t CAS t t RAD RAL t t CAH ASC Column t CWL OEH t ODD t t DZO t t DZC DS Valid Data t OEZ t CLZ t OEA HYB 514400BJ-50/- CRP t ASR Row RWL DRAM SPT03027 1998-10-01 ...
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... RAH t CAH t ASC Column RAD t AWD t CWD t RWD RCS t OEA t DZC t DZO t CAC t CLZ Data OUT t RAC 13 HYB 514400BJ-50/- RSH t CAS CRP t ASR Row t CWL t RWL OEH Valid Data IN t ODD t OEZ 4 DRAM SPT03028 1998-10-01 ...
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... CRP t RHCP t CAS RSH t CAS t CAH t ASC Column t RCS t RRH t CPA OEA OEA t DZC t DZO t t ODD ODD t t OFF t t OEZ OEZ t CAC t CLZ Valid Valid Data OUT Data OUT 4 DRAM t ASR Row t RCH t CDD OFF SPT03029 1998-10-01 ...
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... Column Column t t CWL t CWL WCS t t WCH WCH Valid Valid Data IN Data HYB 514400BJ-50/- DRAM RSH t CRP t CAS t RAL t CAH t t ASC ASR Column Row t RWL t t CWL WCS t WCH ...
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... HYB 514400BJ-50/- RSH t t CAS t RAL t CAH t ASC Column t t CPWD RWL t CWD t CWL t AWD OEA t OEH t CLZ t CPA t t DZC ODD IN Data CAC OEZ Data OUT 1998-10-01 4 DRAM t RP CRP t ASR Row SPT03031 ...
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... V IH RAS CAS ASR V IH Address I/O (Outputs "H" or "L" RAS-Only Refresh Cycle Semiconductor Group RAS t RAH Row HYB 514400BJ-50/- DRAM CRP t RPC t ASR Row SPT03032 1998-10-01 ...
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... ODD V IH I/O (Inputs CDD t OEZ V OH I/O (Outputs OFF "H" or "L" CAS-Before-RAS Refresh Cycle Semiconductor Group t RAS t CHR t CSR t WRH t WRP 18 HYB 514400BJ-50/- DRAM RPC Hi Z 1998-10-01 t CRP SPT03033 ...
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... Semiconductor Group RAS t t RCD RSH t WRP t CAH Column t RRH OEA t DZO t CAC t CLZ t RAC Valid Data OUT 19 HYB 514400BJ-50/- RAS t t CHR CRP t t WRH ASR t CDD t ODD t OFF t OEZ Hi Z 1998-10-01 4 DRAM Row SPT03034 ...
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... V OL "H" or "L" Hidden Refresh Cycle (Early Write) Semiconductor Group RAS RP t RSH t CAH Column t t WCH WRP Valid Data HYB 514400BJ-50/- RAS CHR CRP t ASR WRH 4 DRAM Row SPT03035 1998-10-01 ...
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... RAL t CAH t ASC Column CAC t t WRH RCS t OEA t DZC t DZO t CLZ t WCS t RWL t CWL t WCH t t WRH Data HYB 514400BJ-50/- DRAM t RP RSH t ASR Row t RRH t RCH t CDD t ODD t OFF t OEZ Data OUT SPT03036 1998-10-01 ...
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... IL t ODD V IH I/O1 I/O4 - (Inputs CDD t OEZ V OH I/O1 - I/O4 (Outputs OFF "H" or "L" Test Mode Entry Semiconductor Group RAS CHR t CSR t WTH t WTS 22 HYB 514400BJ-50/- DRAM RPC t CRP t ASR Row Address Hi Z SPT03037 1998-10-01 ...
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... CAS-before-RAS) puts the device into test mode. To exit from test mode, a “CAS-before-RAS refresh”, “RAS-only refresh” or “Hidden refresh” can be used. Addresses A10R, A10C and A0C are don‘t care during test mode. Semiconductor Group HYB 514400BJ-50/-60 8-bits, a test mode cycle using 8:1 4 version the test time DRAM 1998-10-01 ...
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... Index Marking Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 0.2 20x 0.1 0. -0. HYB 514400BJ-50/- DRAM 7.75 -0.25 B 6.8 ±0.3 0.25 B 8.63 -0.25 0.18 B GPJ09100 Dimensions in mm 1998-10-01 ...