at572d740 ATMEL Corporation, at572d740 Datasheet - Page 10

• Manufacturer Part Number: at572d740
• Description: Diopsis 740 Dual Core Dsp
• Manufacturer: ATMEL Corporation

Architectural
Overview
System management
mAgic DSP Processor
Core processor
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AT572D740
DIOPSIS 740 (also named D740) is a high performance dual-core processing platform
for audio, communication and beam-forming applications, integrating a floating-point
DSP (mAgic DSP) and an ARM7TDMI™ Reduced Instruction Set Computer (RISC).
The D740 is optimally suited for floating point applications with a significant need for
complex domain computations like FFT and frequency domain phase-shift algorithms,
requiring high dynamic range and maximum numerical precision.
The D740 combines the flexibility of the ARM7 RISC controller with the very high perfor-
mance of the DSP oriented VLIW architecture of mAgic.
The availability of a standard RISC on-chip lowers software development effort for non
critical and control segments of the application. ARM7TDMI supports the usage of light
RTOS and has efficient interrupt management, leaving mAgic fully available for the
numerically intensive part of the application. The synchronization between the two pro-
cessors can be either based on software polling on semaphores or on interrupts.
The ARM is the D740 master processor. The bootstrap sequence of the D740 starts
from the bootstrap of the ARM from its external non-volatile memory. The ARM then
boots mAgic from a non-volatile memory. After bootstrap the D740 can start its normal
operations. The DSP side of many applications can be implemented on the D740 using
only the internal memory. In fact the program memory size of 8K by 128-bit coupled with
the availability of the code compression, gives an equivalent on-chip program memory
size of about 24K instructions (typical).
The ARM standard In-Circuit Emulation debug interface is supported via the ICE port.
The mAgic DSP is the VLIW numeric processor of the D740. It operates on IEEE 754
40-bit extended precision floating-point and 32-bit integer numeric format. The main
components of the DSP subsystem are the core processor, the on-chip memories and
the interfaces to and from the ARM subsystem. The operators block, the register file, the
address generation unit and the program decoding and sequencing unit compose the
core processor. A short description of each block is given in the following paragraphs.
mAgic is a VLIW engine, but from an user point of view, it works like a RISC machine by
implementing triadic computing operations on data coming from the register file, and
data move operations between the local memories and the register file. The operators
are pipelined for maximum performance. The pipeline depth depends on the operator
used. The operations scheduling and parallelism are automatically defined and man-
aged at compile time by the assembler-optimizer, allowing efficient code execution. In
order to give the best support to the RISC-like programming model, mAgic is equipped
with a complex 256-entry register file. It can be used as a complex register file (real +
imaginary part), or as a dual register file for vectorial operations. When performing sin-
gle instructions the register file can be used as an ordinary 512 register file. Both the left
and right side of the register file are 8-ported, making a total of 16 I/O port available for
the data move to and from the operator block and the memory. The total data bandwidth
between the register file and the operator block is 70 bytes per clock cycle, avoiding bot-
tlenecks in the data flow between the two units.
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