at572d740 ATMEL Corporation, at572d740 Datasheet - Page 12

• Manufacturer Part Number: at572d740
• Description: Diopsis 740 Dual Core Dsp
• Manufacturer: ATMEL Corporation

Internal memories, External
memories and DMA
12
AT572D740
mAgic has four on-chip memory blocks: the Program Memory, the Data Memory, the
Data Buffer, and the dual ported memory shared with the ARM processor.
An External Memory Interface multiplexes the Data accesses and the Program
accesses to and from the External Memory.
The Program Memory stores the VLIW program to be executed by mAgic. It is 8K
words by 128-bit single port memory. When mAgic is in System Mode the ARM can
modify the content of the mAgic Program Memory in two different ways. The ARM can
directly write a Program Memory location by accessing the memory address space
assigned to the mAgic Program Memory in the ARM memory map. In this access mode
the ARM writes four 32-bit words to four consecutive addresses at correct address
boundaries, in order to properly complete a single VLIW word write cycle. The ARM can
also modify the content of the mAgic Program Memory by initiating a DMA transfer from
the External Memory to the mAgic Program Memory. In this access mode a single VLIW
word is transferred from the mAgic External Memory to the mAgic Program Memory 64-
bit per cycle, that is a complete word every two clock cycles. Due to the program com-
pression scheme used, which allows an average program compression between 2 and
3, the code accessing capability of mAgic from its External Memory is greater than an
instruction per clock cycle. When mAgic is in Run Mode, the ARM cannot get access to
the mAgic Program Memory. When in Run Mode mAgic can initiate a DMA transfer
from the External Memory to the mAgic Program Memory to load a new code segment.
The mAgic internal Data Memory is made of three memory pages, 2K words by 40-bit
for the left data memory and 2K words by 40-bit for the right data memory, giving a total
of 6K words for the left and for the right memory banks (a total of 12K words ). Each
Data Memory bank is a dual port memory that allows four simultaneous accesses, two
read and two write. The core can access vectorial and single data stored in the Data
Memory. Accessing complex data is equivalent to accessing vectorial data. During
simultaneous read and write memory accesses, the MAGU generates two independent
read and write addresses common to both the left and the right memory banks. The total
available bandwidth between the Register File and the Data Memory is 20 bytes per
clock cycle, allowing full speed implementation of numerically intensive algorithms (e.g.
complex FFT and FIR).
The Buffer Memory is 2K words by 40-bit for both the left and the right memory. The
Buffer Memory is a dual port memory. A port is connected to the core processor. The
MAGU generates the Buffer Memory addresses for transferring data to and from the
core. The second port of the Buffer Memory is connected to the External Memory Inter-
face. The Buffer Memory does not support dual read and write accesses neither from
the core nor from the External Memory Interface. The available bandwidth between the
core processor and the Buffer Memory is equal to the available bandwidth between the
External Memory Interface and the Buffer Memory: 10 bytes per clock cycle. The maxi-
mum External Memory size of mAgic is 16 Mword Left and Right (equivalent to 32
Mword or 160 Mbytes; 24-bit address bus). A DMA controller manages the data transfer
between the External Memory and the Buffer Memory. The DMA controller can generate
accesses with stride for the External Memory. The DMA transfers to and from the Buffer
Memory can be executed in parallel with the full speed core instructions execution with
zero-overhead and without the intervention of the core processor, except for initiating it.
The last memory block in the address space of the mAgic DSP is the memory shared
(PARM) between mAgic and the ARM processor. It is a dual port memory 512 words by
40- bit for both the left and the right bank (total 1K by 40-bit). This memory can be used
to efficiently transfer data between the two processors. The available bandwidth
between the core processor and the shared memory is 10 bytes per clock cycle. On the
7001AS–DPS–03/04