k4h280838f Samsung Semiconductor, Inc., k4h280838f Datasheet - Page 3

• Manufacturer Part Number: k4h280838f
• Description: 128mb F-die Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM 128Mb F-die (x4, x8)
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Operating Frequencies
*CL : CAS Latency
Ordering Information
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H280438F-TC/LA2
K4H280438F-TC/LB0
K4H280438F-TC/LA0
K4H280838F-TC/LB3
K4H280838F-TC/LA2
K4H280838F-TC/LB0
Speed @CL2.5
Speed @CL2
Part No.
B3(DDR333@CL=2.5)
32M x 4
16M x 8
133MHz
166MHz
Org.
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A2(DDR266@CL=2.0)
Max Freq.
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
133MHz
Interface
SSTL2
SSTL2
Rev. 1.1 May. 2004
A0(DDR200@CL=2.0)
DDR SDRAM
66pin TSOP II
66pin TSOP II
100MHz
Package
-