hcts132ms Intersil Corporation, hcts132ms Datasheet

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hcts132ms

Manufacturer Part Number
hcts132ms
Description
Radiation Hardened Quad 2-input Nand Schmitt Trigger
Manufacturer
Intersil Corporation
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS132MS is a Radiation Hardened Quad 2-Input
NAND Schmitt Trigger inputs. A high on both inputs forces the
output to a Low state.
The HCTS132MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS132MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS132DMSR
HCTS132KMSR
HCTS132D/
Sample
HCTS132K/
Sample
HCTS132HMSR
(Typ)
- VIL = 0.8V Max
- VIH = VCC/2 Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
RAD (Si)/s 20ns Pulse
C
C
C
5 A at VOL, VOH
|
Copyright
o
o
C
C
12
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
o
SCREENING
C to +125
©
RAD (Si)/s
LEVEL
Intersil Corporation 1999
o
-9
C
2
/mg
Errors/Bit-Day
14 Lead SBDIP
14 Lead
Ceramic
Flatpack
14 Lead SBDIP
14 Lead
Ceramic
Flatpack
Die
PACKAGE
500
HCTS132MS
Quad 2-Input NAND Schmitt Trigger
Pinouts
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
(2, 5, 10, 13)
(1, 4, 9, 12)
GND
nO
nA
A1
B1
A2
B2
Y1
Y2
An
H
H
L
L
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
MIL-STD-1835 CDFP3-F14
A1
B1
Y1
A2
B2
Y2
MIL-STD-1835 CDIP2-T14
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Bn
H
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
OUTPUTS
Yn
(3, 6, 8, 11)
H
H
H
L
nY
518604
3062.1
VCC
B4
A4
Y4
B3
A3
Y3

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hcts132ms Summary of contents

Page 1

... Low state. The HCTS132MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS132MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART TEMPERATURE ...

Page 2

... VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.5V, (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS132MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 3

... SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC = 4.5V, VIN = VCC or GND, (Source) VOUT = VCC -0.4V Specifications HCTS132MS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 10, 11 +125 9 10, 11 +125 ...

Page 4

... PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised. Specifications HCTS132MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour TABLE 6 ...

Page 5

... Each pin except VCC and GND will have a resistor of 1K OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS132MS TABLE 7. TOTAL DOSE IRRADIATION TEST PRE RAD POST RAD ...

Page 6

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS132MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 7

... AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS132MS AC Load Circuit DUT TPHL CL = 50pF RL = 500 TTHL 80% 20% UNITS 506 TEST POINT CL RL 518604 Spec Number ...

Page 8

... Metallization Mask Layout Y1 (3) A2 (4) B2 (5) NC NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS132 is TA14483A. HCTS132MS HCTS132MS VCC (2) (1) (14) (13) ...

Page 9

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HCTS132MS EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...

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