hcts10dmsr Intersil Corporation, hcts10dmsr Datasheet

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hcts10dmsr

Manufacturer Part Number
hcts10dmsr
Description
Radiation Hardened Triple 3-input Nand Gate
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Current Levels Ii
Description
The Intersil HCTS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
The HCTS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS10MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS10DMSR
HCTS10KMSR
HCTS10D/
Sample
HCTS10K/
Sample
HCTS10HMSR
(Typ)
- LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
|
o
o
C
C
Copyright
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
LEVEL
C to +125
©
RAD (Si)/s
Intersil Corporation 1999
o
-9
C
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
2
/mg
Errors/Bit-Day
PACKAGE
1
Pinouts
Functional Diagram
NOTE: L = Logic Level Low, H = Logic level High
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C
HCTS10MS
GND
(5, 11, 13)
(2, 4, 10)
A1
B1
A2
B2
C2
Y2
(1, 3, 9)
An
Bn
Cn
An
H
H
H
H
L
L
L
L
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
A1
B1
A2
B2
C2
Y2
Triple 3-Input NAND Gate
Bn
H
H
H
H
L
L
L
L
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Cn
H
H
H
H
L
L
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
10
11
9
8
VCC
C1
Y1
C3
B3
A3
Y3
OUTPUTS
Yn
H
H
H
H
H
H
H
L
(6, 8, 12)
Yn
518778
2434.2
VCC
C1
Y1
C3
B3
A3
Y3

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hcts10dmsr Summary of contents

Page 1

... This device is a member of radia- tion hardened, high-speed, CMOS/SOS Logic Family. The HCTS10MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART TEMPERATURE SCREENING NUMBER RANGE o o HCTS10DMSR - +125 C Intersil Class S Equivalent o o HCTS10KMSR - +125 C ...

Page 2

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 3

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input to Output TPHL VCC = 4.5V TPLH VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = 500 , CL = 50pF, Input TR ...

Page 4

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B ...

Page 5

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONDITIONS (Note 10, 11, 13 STATIC BURN-IN II TEST CONNECTIONS (Note ...

Page 6

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 7

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS10MS AC Load Circuit TPHL TTHL 80% ...

Page 8

Die Characteristics DIE DIMENSIONS mils 2.20 x 2.24mm METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND ...

Page 9

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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