hcts540ms Intersil Corporation, hcts540ms Datasheet

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hcts540ms

Manufacturer Part Number
hcts540ms
Description
Rad-hard Inverting Octal Buffer/line Driver, Three-state
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS540MS is a Radiation Hardened inverting
Octal Buffer/Line Driver, with two active-low output enables.
The output enable pins (OE1 and OE2) control the three-
state outputs. If either enable is high the outputs will be in
the high impedance state. For data output both enables
(OE1 and OE2) must be low.
The HCTS540MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS540MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS540DMSR
HCTS540KMSR
HCTS540D/Sample
HCTS540K/Sample
HCTS540HMSR
Bit-Day (Typ)
- Bus Driver Outputs 15 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
Inverting Octal Buffer/Line Driver, Three-State
/mg
-9
o
o
C
C
Errors/
1
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS540MS
GND
OE1
SCREENING LEVEL
A0
A1
A2
A3
A4
A5
A6
A7
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
OE1
A0
A1
A2
A3
A4
A5
A6
A7
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
Spec Number
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
File Number
PACKAGE
518631
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2232.2

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hcts540ms Summary of contents

Page 1

... OE2) must be low. The HCTS540MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS540MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...

Page 2

... Functional Diagram INPUTS ( OE1 1 OE2 19 OE1 H = High Level L = Low Level X = Don’t Care Z = High Impedance HCTS540MS ONE OF 8 BUFFERS TRUTH TABLE OE2 OUTPUTS ( OTHER 7 BUFFERS OUTPUT Spec Number ...

Page 3

... VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.8V (Note 2) NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS540MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC Output Current (Sink) IOL Output Current IOH (Source) Output Voltage Low VOL Specifications HCTS540MS GROUP (NOTES SUB- CONDITIONS GROUPS ...

Page 5

... PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised. 2. Table 5 parameters only. Specifications HCTS540MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour 5 TABLE 6 ...

Page 6

... Each pin except VCC and GND will have a resistor of 680 OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS540MS TABLE 7. TOTAL DOSE IRRADIATION TEST PRE RAD POST RAD ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS540MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... Three-State Low Timing Diagrams VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 0.90 VIL 0 GND 0 HCTS540MS AC Load Circuit DUT TPHL CL = 50pF RL = 500 TTHL 80% 20% UNITS Three-State Low Load Circuit TPLZ VW UNITS ...

Page 9

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HCTS540MS Three-State High Load Circuit DUT TPZH CL = 50pF 500 UNITS ...

Page 10

... A1 (3) A2 (4) A3 (5) A4 (6) A5 (7) A6 (8) NOTE: The die diagram is a generic plot form a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS540 is TA14455A. HCTS540MS HCTS540MS A0 OE1 VCC OE2 (2) (1) (20) (19) ...

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