hcts541ms Intersil Corporation, hcts541ms Datasheet

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hcts541ms

Manufacturer Part Number
hcts541ms
Description
Rad-hard Non-inverting Octal Buffer/line Driver, Three-state
Manufacturer
Intersil Corporation
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS541MS is a Radiation Hardened non-
inverting octal buffer/line driver, three-state outputs. The
output enable pins (OEN1 and OEN2) control the three-state
outputs. If either enable is high the outputs will be in the high
impedance state. For data output both enables (OEN1 and
OEN2) must be low.
The HCTS541MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS54 is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS541DMSR
HCTS541KMSR
HCTS541D/Sample
HCTS541K/Sample
HCTS541HMSR
Bit-Day (Typ)
- Bus Driver Outputs - 15 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
682
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS541MS
Octal Buffer/Line Driver, Three-State
GND
OE1
A0
A1
A2
A3
A4
A5
A6
A7
SCREENING LEVEL
Radiation Hardened Non-Inverting
FLATPACK PACKAGE (FLATPACK)
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
OE1
A0
A1
A2
A3
A4
A5
A6
A7
MIL-STD-1835 CDFP4-F20
MIL-STD-1835 CDIP2-T20
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
Spec Number
11
File Number
PACKAGE
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
518630
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3073.1

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hcts541ms Summary of contents

Page 1

... Input Current Levels VOL, VOH Description The Intersil HCTS541MS is a Radiation Hardened non- inverting octal buffer/line driver, three-state outputs. The output enable pins (OEN1 and OEN2) control the three-state outputs. If either enable is high the outputs will be in the high impedance state ...

Page 2

... Functional Block Diagram TTL 2 TTL 3 TTL 4 TTL 5 TTL 6 TTL 7 TTL 8 TTL 1 19 TTL OE1 High Voltage Level Low Voltage Level Immaterial High Impedance HCTS541MS VDD TTL TRUTH TABLE INPUTS OE2 ...

Page 3

... VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.8V (Note 2) NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS541MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCTS541MS GROUP (NOTES 1, 2) ...

Page 5

... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH IOZL/IOZH Specifications HCTS541MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT ...

Page 6

... Each pin except VCC and GND will have a resistor of 680 OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS541MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS541MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... Three-State Low Timing Diagrams VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 0.90 GND 0 HCTS541MS AC Load Circuit TPHL TTHL 80% 20% UNITS Three-State Low Load Circuit TPLZ VW UNITS 689 DUT TEST ...

Page 9

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HCTS541MS Three-State High Load Circuit DUT TPHZ VW UNITS V V ...

Page 10

... A3 (5) A4 (6) A5 (7) A6 (8) NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS541 is TA14456A. HCTS541MS HCTS541MS 691 (18) Y0 (17) Y1 (16) Y2 (15) Y3 (14) Y4 (13) Y5 ...

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