mk60dn512zvll10 Freescale Semiconductor, Inc, mk60dn512zvll10 Datasheet - Page 57
mk60dn512zvll10
Manufacturer Part Number
mk60dn512zvll10
Description
Up To 100 Mhz Arm Cortex-m4 Core With Dsp
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MK60DN512ZVLL10.pdf
(75 pages)
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6.8 Communication interfaces
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Freescale Semiconductor, Inc.
Symbol
MII1
MII2
MII3
MII4
MII5
MII6
MII7
MII8
—
—
RXCLK frequency
RXCLK pulse width high
RXCLK pulse width low
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
TXCLK pulse width high
TXCLK pulse width low
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
Description
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 38. MII signal switching specifications
Preliminary
Peripheral operating requirements and behaviors
35%
35%
35%
35%
Min.
—
—
—
5
5
2
Max.
65%
65%
65%
65%
25
25
25
—
—
—
RXCLK
RXCLK
TXCLK
TXCLK
period
period
period
period
MHz
MHz
Unit
ns
ns
ns
ns
57