mk60dn512zvll10 Freescale Semiconductor, Inc, mk60dn512zvll10 Datasheet - Page 74

• Manufacturer Part Number: mk60dn512zvll10
• Description: Up To 100 Mhz Arm Cortex-m4 Core With Dsp
• Manufacturer: Freescale Semiconductor, Inc

Revision History
74
Rev. No.
2
3
4
5
3/2011
3/2011
3/2011
6/2011
Date
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Many updates throughout
Added sections that were inadvertently removed in previous revision
Reworded I
Added paragraph to "Peripheral operating requirements and behaviors" section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
Substantial Changes
Table 50. Revision History (continued)
• Changed supported part numbers per new part number scheme
• Changed DC injection current specs in "Voltage and current operating requirements"
• Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage
• Split Low power stop mode current specs by temperature range in "Power
• Changed typical I
• Added ENET and LPTMR clock specs to "Device clock specifications" table
• Changed Minimum external reset pulse width in "General switching specifications"
• Changed PLL operating current in "MCG specifications" table
• Added footnote to PLL period jitter in "MCG specifications" table
• Changed Supply current in "Oscillator DC electrical specifications" table
• Changed Crystal startup time in "Oscillator frequency specifications" table
• Changed Operating voltage in "EzPort switching specifications" table
• Changed title of "FlexBus switching specifications" table and added Output valid and
• Added "FlexBus full range switching specifications" table
• Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table
• Changed Gain spec in "16-bit ADC with PGA characteristics" table
• Added typical Input DC current to "16-bit ADC with PGA characteristics" table
• Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA
• Changed Analog comparator initialization delay in "Comparator and 6-bit DAC
• Changed Code-to-code settling time, DAC output voltage range low, and Temperature
• Changed Temperature drift and Load regulation in "VREF full-range operating
• Changed Regulator output voltage in "USB VREG electrical specifications" table
• Changed I
• Changed DSPI_SCK cycle time specs in "DSPI timing" tables
• Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table
• Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high-
• Changed Reference oscillator current source base current spec and added Low-
table
and current operating behaviors" table
consumption operating behaviors" table
table
hold specs
characteristics" table
electrical specifications"
coefficient offset voltage in "12-bit DAC operating behaviors" table
behaviors" table
speed mode)" table
power current adder footer in "TSI electrical specifications" table
IC
footnote in "Voltage and Current Operating Requirements" table.
LIM
description and specs in "USB VREG electrical specifications" table
DD_VBAT
Preliminary
spec in "Power consumption operating behaviors" table
Freescale Semiconductor, Inc.