vp101-5bahp Zarlink Semiconductor, vp101-5bahp Datasheet - Page 8
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vp101-5bahp
Manufacturer Part Number
vp101-5bahp
Description
30/50mhz 8-bit Cmos Video Dac
Manufacturer
Zarlink Semiconductor
Datasheet
1.VP101-5BAHP.pdf
(10 pages)
PCB LAYOUT CONSIDERATIONS
great care must be taken in the PCB layout to ensure low
noise power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Power and Ground Planes
own power/ground planes connected at a single point
through a ferrite bead. It is important that the regular PCB
and ground planes do not overlay any portions of the analog
power or ground planes to minimise plane-to-plane noise
coupling.
Digital Signal Interconnect
as much as possible from the analog circuitry. Due to the
high clock rates used, the clock lines to the VP101 should be
as short as possible to minimise noise pickup.
connected to the regular PCB power plane, not to the analog
power plane.
To obtain the optimum performance from the VP101
The VP101 and its associated circuitry should have its
The digital signal lines to the VP101 should be isolated
Any pull-up resistors used on the inputs should be
Fig.5 VP101 typical connections
Supply Decoupling
by the use of multiple decoupling capacitors (See Fig. 5).
ceramic capacitors placed as close as possible to the V
pins, with the shortest leads possible to reduce lead
inductance.
of the VP101 will reject power supply noise, this rejection
decreases with frequency. Any high frequency noise on the
regular supply (such as produced by a switch mode power
supplies) must be adequately suppressed, else the designer
should consider using a three terminal regulator to supply
the analog power plane.
Analog Signal Interconnect
and source termination resistors should be as close as
possible to the VP101 to minimise noise pickup and
reflections due to impedance mismatch. The video out
signals should overlay the ground plane and not the analog
power plane, to maximise the high frequency power supply
rejection.
Noise on the analog power plane will be further reduced
Optimum performance is obtained with 0.1 F chip
It should be noted that while the loop amplifier circuitry
For optimum performance the analog output connectors
VP101
AA
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