mt58l512v18p ETC-unknow, mt58l512v18p Datasheet - Page 3

• Manufacturer Part Number: mt58l512v18p
• Description: 512k 256k 32/36 Pipelined, Syncburst Sram
• Manufacturer: ETC-unknow

GENERAL DESCRIPTION (continued)
(GW#). Note that CE2# is not available on the
T Version.
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
Address and write control are registered on-chip to
3
PIPELINED, SCD SYNCBURST SRAM
DQc pins and DQPc; BWd# controls DQd pins and
DQPd. GW# LOW causes all bytes to be written. Parity
bits are only available on the x18 and x36 versions.
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
of clock.
+3.3V V
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium
and PowerPC pipelined systems and systems that ben-
efit from a very wide, high-speed data bus. The device
is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
sramds) for the latest data sheet.
TQFP PINOUTS
two pinouts in the industry. Micron will support both
pinouts for this part.
This device incorporates a single-cycle deselect fea-
Micron’s 8Mb SyncBurst SRAMs operate from a
Please refer to Micron’s Web site
At the time of the writing of this data sheet, there are
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
power supply, and all inputs and outputs are
t
KQHZ nanoseconds after the rising edge
(www.micron.com/
©2002, Micron Technology, Inc.